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6.1.4.
Control Block (ASIC)
The system uses an ASIC called iVDC (Intelligent Voice & Peripheral Device Controller), which comprises the voice processing
engine of the PCC voice mail system, run in combination with an SH microprocessor and TI DSPs. This ASIC allows the
sending and receiving of 24 channels of audio serial data with 12 DSPs and enables data exchange with the HDD through
buffer memory. Necessary logic is imbedded to control other peripheral devices, HDLC, and VM-Link interfaces.
Module in iVDC and Function
Module Name
Serial Communication Clock Module
VM-Link Interface Module
VM-Link Interface Module
HDLC Module
SRAM Interface Module
Host CPU Interface Module
Cch Interrupt Control Module
DSP Control Module
iVDC Terminal Name and Number
System Terminal
SH-CPU Interface Terminal (Access Control Terminal)
SH-CPU Interface Terminal (Interrupt Terminal)
External Device Control Terminal (General-purpose Port)
External Device Control Terminal (External Chip Select)
External Device Control Terminal (HDD Interface)
External Device Control Terminal (DSP)
External Device Control Terminal (DPT (ECO) )
SRAM Interface Terminal
McBSP0 Timing Control Terminal
McBSP1 Timing Control Terminal
VM-Link Interface Terminal
McBSP0 Data (VM-Link Bridge)
McBSP1 Data
HDLC External Connection Terminal
Cch Interrupt
Mode Terminal and User Test Terminal
JTAG Terminal
iVDC Specification
Wafer manufacturer
ASIC specification
Number of pins
Power-supply voltage
Package
Operating frequency
Terminal Descriptions
System Terminal
N_PRST
SYSCLK
SH-CPU interface terminal (access control terminal)
N_IVDC_CS
N_CE1A
N_CE2A
N_CE1B
N_RD
N_WE
RD_NWR
N_WAIT
LA22 - LA1
LD15 - LD0
Generates bus timing of three types of McBSP0 based interfaces (DPT, APT, VM-Link).
Generates bus timing of McBSP1 based interfaces.
PBX interface function and bridge function with McBSP0.
Communicates with DSP through McBSP1. Sends and receives the compressed voice data. Controls
voice data by the voice buffer interrupt.
HDLC function consisting of serial packet switching managing Bch and Dch HDLC and their host
points.
Manages timing of SRAM for external connection voice buffer.
Access to the CPU control register group, voice buffer access, external device access control,
addressing of external devices such as DSP, ECO, LAN, and USB.
Cch interrupt function during DPT.
Manages and controls DSP interrupt.
Terminal Name
Development code name
input
"L"Act
input
posedge System clock. 65.536MHz
input
"L"Act
input
"L"Act
input
"L"Act
input
"L"Act
input
"L"Act
input
"L"Act
input
"L"Act
output
"L"Act
input
-
inout
-
Function
iVDC
Fujitsu
0.35 µm Embeded Cell Arrays
256
+3.3V
QFP
65.536MHz for logics and PCM clocks
Power-on reset signal. Asynchronous input for system reset.
Chip select signal (Area 4:iVDC)
Chip select signal (Area 5 low-order byte)
Chip select signal (Area 5 high-order byte)
Chip select signal (Area 6 low-order byte)
"Read strobe"
Write strobe
Read/write status
Wait signal
CPU address input
CPU data bus
37
KX-TVM200E / KX-TVM200NE
Number of Terminals
2
47
4
6
3
2
30
16
39
13
14
4
2
2
4
2
3
5
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