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TEST1
JTAG terminal
TRST
TMS
TCK
TDI
TDO
Additional power supply terminal
ADD_VDD_0001
ADD_VDD_0012
ADD_VSS_0001
ADD_VSS_0011
input
-
User test signal. Used when testing SIC chip. "L"=normal operation.
"H"= test mode.Test mode has the following actions.
• • • • The input clock frequency is treated as 32MHz. Normally, 64MHz is
input to the SYSCLK terminal and clock inputs are provided by
dividing by 2 for 32MHz internal clocks and 4 for 16MHz internal
clocks. In test mode, the SYSCLK input is passed directly at
32MHz.
Input frequency is then divided by 2 for 16MHz clocks.
• • • • The reset of the test register is released. The test register is usually
reset so that values are not writable.
input
-
TEST Reset
input
-
TEST Mode Select
input
-
TEST Clock
input
-
TEST Data (IN)
output
-
TEST Data (OUT)
output
-
Additional VDD, 3.3V. Treated as output at the logic design level.
output
-
Additional GND, 0V. Treated as output at the logic design level.
39
KX-TVM200E / KX-TVM200NE
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