Sony CXD5602 User Manual page 869

Also, the possibility of a large delay longer than the sampling period is:
Condition:
Sampling frequency change (Low => High) (SAMP_RATIO High => Low)
The current count value Count value at register change > (2^RPOST-1)
Possibility of occurrence:
1-1/(RPRE/RPOST)
3.9.15.15 HPADC CIC Filter Parameter Dynamic Change
When performing sampling rate conversion using the CIC filter within the ADCIF, a maximum delay equal to
the [original sampling period of the HPADC analog region] x 256 will occur when the sampling rate is
dynamically changed to a higher rate than the one currently in use.
This is because the CIC filter uses the same counter circuit as the sample decimation circuit of the LPADC
(Section 3.9.15.14).
3.9.15.16 Decimation Partition Write FIFO and Read FIFO Connection
Combinations
In principle, the Write FIFOs and Read FIFOs of the decimation partition must be connected in a one-to-one
relation as shown in the example in Figure SCU (Sensor Control Unit)-94.
One-to-N connections as shown in Figure SCU (Sensor Control Unit)-95 are functionally capable of realizing
equivalent processing by one-to-one connections but they are normally not used.
SEQ0
Decimation
Decimation
Decimation
Figure SCU (Sensor Control Unit)-94 1 One-to-One Connection (Example)
SEQ0
Decimation
Decimation
Decimation
Figure SCU (Sensor Control Unit)-95 One-to-N Connection (Example)
D0_W0_S D0_R0_H
D0_W1_S D0_R1_C
D0_W2_S D0_R2_C
D0_W3_S D0_R3_CH
D0_W0_S
D0_W1_S
D0_W2_S
D0_W3_S
－869/1010－
SEQ0
Decimation
Decimation
Decimation
D0_R0_H
D0_R1_C
D0_R2_C
D0_R3_CH
CXD5602 User Manual
D0_W0_S D0_R0_H
D0_W1_S D0_R1_C
D0_W2_S D0_R2_C
D0_W3_S D0_R3_CH