Sony CXD5602 User Manual page 965

3.21.10 Performance Estimation
The following describes the performance estimation of the maximum sampling frequency.
SCU Main Resource/Mode
Clock(Hz)
32,768 LPADC/1CH
LPADC/2CH
LPADC/4CH
HPADC
8,192,000 LPADC/1CH
LPADC/2CH
LPADC/4CH
HPADC
13,000,000 LPADC/1CH
LPADC/2CH
LPADC/4CH
HPADC

The following describes the sensor conditions with sensor operation.
・Six byte read transfer per event for each sensor (three axes are assumed)
・The total of the sampling frequencies of all SPI sensors is 820 Hz (1 Hz when the clock is 32 kHz)
・The total of the sampling frequencies of all I2C sensors is 180 Hz (1 Hz when the clock is 32 kHz)
・The SPI's transfer rate is about 4 Mbps, and the I2C's transfer rate is about 400 Kbps (The SPI's is
about 16Kbps, and the I2C's is about 1.4 Kbps, when the clock is 32 kHz)
Caution: When you use the XOSC for sampling clock of the ADC, set the decimation filter so that the frequencies
are less than the supported frequencies shown above.
In the meantime, the following describes the worst cases of the sensors estimated on the typical HPADC/LPADC
scenario.
Table ADC-778 ADC Sampling Frequency Estimation
With Sensor Operation
(Hz)
25
15
8
90
5,500
512
256
22,000
9,500
512
256
37,000
－965/1010－
Without Sensor Remarks
Operation (Hz)
27
17
9
100
6,500
512 ADC
bottleneck
256 ADC
bottleneck
26,000
11,000
512 ADC
bottleneck
256 ADC
bottleneck
41,000
CXD5602 User Manual
HW performance
HW performance
HW performance
HW performance