Sony CXD5602 User Manual page 943

0x041004DC CKDIV_COM
CK_APB RW [25:24]
Reserved RO [23:19]
CK_AHB RW [18:16]
Reserved RO [15:5]
CK_M0 RW [4:0]
Reserved RO [31:5]
－943/1010－
2'b00
Indicated as DIV(2) in
Reset Control-116
Frequency division setting (ratio against AHB clock)
of APB clock
0: divided by 1
1: divided by 2
2: divided by 4
4: divided by 8
0 Reserved
0
Indicated as DIV(1) in
Reset Control-116
Frequency division setting (ratio against CPU clock)
of AHB clock
0: divided by 1
1: divided by 2
2: divided by 4
3: divided by 8
4: divided by 6
5, 6, 7: Prohibited settings
0 Reserved
0
Indicated as DIV(0) in
Reset Control-116
Frequency division setting (ratioagainst ck_cpu_bus)
of System and I/O Processor
0: divided by 1
1: divided by 2
...
30: divided by 31
31: divided by 32
0 Reserved
CXD5602 User Manual
Figure SYSIOP Clock and
Figure SYSIOP Clock and
Figure SYSIOP Clock and