Sony CXD5602 User Manual page 960

RCOSC
1/250
8.192MHz
CKSEL_SCU.SEL_SCU_32K
XOSC
CKSEL_SCU.SCU_XTAL
Clocks supplied to the HPADC and the LPADC are controlled by the following register.
Control from Block Name
CPU TOPREG
For EN(1) and EN(2) in Figure ADC-120, and the summary of clock source selection, refer to Section of the
Clock Control described in Chapter of the SCU (3.9).
3.21.5.2 Clock for the LPADC

CK_SCU_U32KL
This is a clock to determine the sampling frequency of the LPADC.
CK_SCU_U32KL is generated in the CRG (Clock Reset Generator), and it is divided CK_SCU_32K (low speed
logic system clock) by 2^n (n = 0 to 15). For the range of the available sampling frequencies, refer to Table
ADC-810.
The API enables to select clock sources and to control selecting division ratio of CK_SCU_U32KL.
RCRTC
0
RTC 1
DIV
"configure unavailable"
CKSEL_SCU.SEL_SCU
Figure ADC-120 Schematic Diagram of the Clock Control
Table ADC-774 Clock Control Register List
Register Name
SCU_CKEN
CKDIV_SCU.SCU_32KH
CK_SCU_U32KH
DIV CG
SCU_CKEN[7]
CK_SCU_RC8M
CK_SCU_XOSC
CKDIV_SCU.SCU_32KL
DIV CG
SCU_CKEN[6]
0
EN(1)
1
CG
2 CK_SCU_SCU_SC
CG
3
EN(2)
for GNSS TADC
for CK_SCU_SPI
CK_SCU_I2C0
Offset Comment
0x071c TOPREG control area
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CXD5602 User Manual
HPADC
HPAD_LV_CLK_U32
HPAD_LV_CLK_RC8M
HPAD_LV_CLK_XOSC
DIV
LPADC
CK_SCU_U32KL
LPAD_LV_CLK
ADCIF
CK_SCU_SCU
etc..