HP 3478A Technical Manual page 113

3478A 3478A
2. 2. Si Sinc nce t e the n he neg
connected to BT701, the output of connected to BT701, the output of the comparator
attempts to go attempts to go high and charges capac high and charges capacitor C763.
output goes high since the comparator has an open output goes high since the comparator has an open
collector output and a pull-up resistor is connected collector output and a pull-up resistor is connected
between the CPU's RESET line (output of USSOC between the CPU's RESET line (output of USSOC and
U5SOD) and + 5V (the resistor is internal to the CPU). U5SOD) and + 5V (the resistor is internal to the
3. 3. Du Duri ring t ng the c he cha
held low until the capacitor is charged to a high level. held low until the capacitor is charged to a
4. 4. The RE The RESE SET l
resets and turns on. resets and turns on. The 3478A is now in its The 3478A is now in its turn-on state.
5. 5. As l As lon ong as g as th the RE
SS (Single Step) line is low (the line is connected to the SS (Single Step) line is low (the l
RESET line). The SS line steps the RESET line). The SS line steps the CPU to its first
program line. program line. The program line s The program line sets the PSEN line high,
which disables the Control which disables the Control ROM (CE high).
the ROM from operating until the CPU turns on. the ROM from operating until the CPU turns on.
6. 6. When t Wh en the R he RES
the CMOS RAM (U512) is also low and disables the RAM the CMOS RAM (U512) is also low
(see paragraph 7-F-61). (see paragraph 7-F-61).
7. 7. The C Th e CPU PU is a is als lso r
supply goes low. A low + 5V sets th supply goes low. A low + 5V sets the positive in-put of
U550C low which m U550C low which makes U55OC's out akes U55OC's output low.
the CPU. the CPU.
b. b. Reset Circuitry Reset Circuitry. . Refer
Schematic 3 and 4. The Reset Circuitry is Schematic 3 and 4. The Reset Circuitry is used to reset
the CPU when the TEST/RESET button is pressed or if the CPU when the TEST/RESET button is pressed or if
the CPU inadvertently goes to a non-operational state. the CPU inadvertently goes to a non-operational state.
The step by step operation is as follows: The step by step operation is as follows:
1. 1. Dur During n ing norm ormal ope al operat
continuously incremented by the ALE clock. continuously incremented by the ALE clock.
2. 2. Por Port P15 (U t P15 (U501 pi 501 pin 32) co
Figure 7-F-19. Figure 7- F-19. Reset Reset Circuitry Circuitry
egat ativ ive te e term rmin inal o al of US f USSO SOC is
the comparator
itor C763. The
harg rge t e tim ime, e, th the RE e RESE SE'I l 'I lin ine is
high level.
T line ine go goes es hi high gh an and t d the he CP
turn-on state.
e RESE SET li T line i ne is lo s low, t w, the C
ine is connected to the
CPU to its first
ets the PSEN line high,
ROM (CE high). This prevents This prevents
ESET l ET lin ine is e is lo low, t w, the C he CE2 l
and disables the RAM
o res eset et wh when en th the + 5 e + 5V po
e positive in-put of
put low. This resets This resets
Refer t t o Figure 7-F-19 o Figure 7-F-19, or
used to reset
ration ion, cou , counte nter U50 r U507 is 7 is
n 32) conti ntinuo nuousl usly out y output d
C is to the keyboard (P15 is one port used to scan the to the keyboard (P15 is one port used to scan the
keyboard, see par keyboard, see paragraph 7-F-65).
The as long as the key as long as the keyboard is scanned.
developed from P15 using C501 and R528. developed from P15 using C501 and R528.
and
CPU). CPU goes to a non-operational state, the keyboard CPU goes to a
scanning is stopped. scanning is stopped.
e is
counter keeps incrementing for about 1.3 seconds. counter keeps incrementing for about 1.3 seconds.
CPU U
goes high (RESET goes high (RESET REQ line goes h
he CPU PU's 's the counter is not being reset. the counter is not being reset.
terminal of comparator U750D. terminal of com
U750D low which in turn brings the RESET U750D low which in turn brings the RESET line low.
E2 line ine of of stops incrementing. stops incrementing.
U750D attempts to go high and charges C763 (see step a- U750D attempts to go high and charges C763 (see step a-
V powe wer r 2). 2).
level, the RESET line once again level, the RESET
then resets and then resets and turns on.
, or state. state.
7-F 7-F-60 -60. . CMO
the 3478A'S Calibration Constant the 3478A'S
paragraphs explain how the RAM is addressed, how data paragraphs explain how the RAM is addressed, how data
(constants) is read from the RAM, and how new data (new (constants) is read from the RAM, and how new data (new
constants) is sen constants) is sent to the RAM.
RAM's Address, Input, and Output Lines RAM's Address, In
Lines are connected to the CPU's lower 8 Address bits Lines are connected to the CPU's lower 8 Address bits
put data ata (AO to A7). (AO to A7). The RAM's input and
are connected to each other and to the DO to D3 Data are connected to each other and to the DO to D3 Data
Lines. Lines.
7-F-61. 7-F- 61. RAM
addressed as long as line CE2 (Chip Enable 2 at U512 pin addressed as long as line CE2 (Chip Enable
17) is high. The line is high when the 17) is high.
Line CEI (Chip Enable I at U512 Line CEI (Chip Enable I at U512 pin 19) can be high or
low. This line is used to rea low. This line is used to read the RAM (see n
paragraph). paragraph).
7-F-62. 7-F- 62. Readin
the following conditions. the following conditions.
a. a. Line OD (Output Disable at Line OD (Output Disable at U512 pin 18) must
low. low. It is low when the It is low when the RD Line (Read at US01 pin
low. low.
b. b. Line CEI Line CEI must also
one section of the Quad flip-flop U506 (pin 6). one section of the Quad flip-flop U506 (pin 6).
7-F-18 7-F-18
agraph 7-F-65). This resets the c
board is scanned. The reset pulse is
3. 3. If the T If t he TES EST/ T/RE RESE SET bu T butt tton i
non-operational state, the keyboard
4. 4. Sin Since t ce the A he ALE c LE cloc lock is s
5. 5. Af Afte ter th r the 1. e 1.3 se 3 seco cond nds, t
REQ line goes high).
6. 6. Th The Q o e Q out utpu put is t is co conn
parator U750D. This brings the outpu
7. 7. Th The A e ALE LE cl cloc ock t k tur urns ns of off a
8. 8. Th The Q o e Q out utpu put g t goe oes l s low
9. 9. On Once t ce the c he cap apac acit itor i or is ch
line once again goes high.
turns on. The 3478A is nowin its tu The 3478A is nowin its turn-on
CMOS RA S RAM M . . The CMOS RAM The CMOS RAM is used to
Calibration Constants. s. The following
t to the RAM. This is done using the This is done using the
put, and Output Lines. . The Address
The RAM's input and output lines (DO to D3)
RAM Addre Addressing ssing. . The RAM The RAM can only
The line is high when the 3478A is turned on.
d the RAM (see next
Reading t g the he RAM RAM. . The RAM can The RAM can be read unde
RD Line (Read at US01 pin 9) is
must also be low. be low. It receives
TM 11-6625-3071-14 TM 11-6625-3071-14
This resets the counter ounter
The reset pulse is
on is pr s pres esse sed or t d or the he
k is sti till o ll ope pera rati ting ng, th , the e
s, the Q o he Q out utpu put of U t of U50 507 7
igh). This is because This is because
nnec ecte ted to d to th the ne e nega gati tive ve
This brings the output of t of
line low.
f and nd th the c e cou ount nter er
ow an and t d the he ou outp tput ut of of
s char arge ged to d to th the hi e high gh
goes high. The CPU The CPU
rn-on
is used to store store
The following
The Address
output lines (DO to D3)
can only be be
2 at U512 pin
3478A is turned on.
pin 19) can be high or
ext
be read under r
U512 pin 18) must be be
9) is
It receives the low the low from from