HP 3478A Technical Manual page 114

3478A 3478A
The flip-flop operates like a latch and transfers data from The flip-flop operates like a latch and transfers data from
Port P23 during each ALE cycle. Port P23 during each ALE cycle.
c. c. Once the previous con Once the previous conditions are met (t
addressed) and line CE2 is high, data from the RAM is addressed) and line CE2 is high, data from the RAM is
transferred to the Data Lines. transferred to the Data Lines.
7-F-63. 3. Sendin 7-F-6 Sending Data g Data to the to the RAM
receive new Data when its R/W line (Read/Write at U5 receive new Data when its R/W line (Read/Write at U5
12 pin 20) is low. 12 pin 20) is low. This can only happen if This can only happen if the 3478A's
Cal Enable Switch (located on the front panel) is on and Cal Enable Switch (located on the front panel) is on
the WR line of the CPU the WR line of the CPU (Write at U501 pin 10) is low.
The following explains the operation. The following explains the operation.
a. a. The C The Cal En al Enabl able Swi e Switch b
gate U508C low. gate U508C low.
b. b. The o The othe ther inp r input of ut of the g
line. line.
c. c. The o The outp utput of ut of U50 U508C go
gate U508D is configured as an inverter, the output of gate U508D is configured as an inverter, the output of
U508D goes low. The RAM is now ready U508D goes low. The RAM is now ready to receive new
data. data.
7-F-64. Since the 7-F-64. Since the 3478A's Calibration 3478A's Calibration Constants
stored in the CMOS RAM, the constants must remain in stored in the CMOS RAM, the constants must remain in
the RAM when the 3478A is turned off (or power the RAM when the 3478A is turned off (or power
removed). This is done by batt removed). This is done by battery BT701 in the +
Power Supply Circuit. In addition, the RAM Power Supply Circuit. In addition, the RAM should not
see any possible write commands (R/W low) during the see any possible write commands (R/W low) during the
time that power is removed. time that power is removed. The RAM must b
This is because a write command may erase some This is because a write command may erase some
calibration constants. . The RAM is calibration constants The RAM is disabled by
comparator U750C (part of the CPU's power-on circuit in comparator U750C (part of the CPU's power-on circuit in
the + 5V power supply). . The operation is as f the + 5V power supply)
(refer to Schematic 4 for the explanation): (refer to Schematic 4 for the
a. a. As lo As long as ng as the the 347 3478A is
supply voltage from Q701. supply voltage from Q701.
b. b. Whe When po n power i wer is off s off, th
voltage from battery BT701 through voltage from batt ery BT701 through diode CR764.
battery voltage is used for data retention. battery voltage is used for
c. c. Aft After tu er turni rning po ng power o
setting Line CE2 setting Line CE2 low. low. This is done This is done by comparato
U750C. The comparator s U750C. The comparator senses a low (or no
voltage divider R761 voltage divider R761, R762, and , R762, and R763.
negative terminal is at the battery voltage, the output of negative terminal is at the battery voltage, the output of
U70SOC becomes low. U70SOC becomes low. This makes line
disables the RAM. disables the RAM.
7-F-65. 5. Keybo 7-F-6 Keyboard ard Opera Operation
pushbuttons are connected in a 4x4 matrix and are pushbuttons are connected in a 4x4 matrix and are
continuously scanned continuously scanned by the CPU. by the CPU. The operation
follows: follows:
a. a. One s One side o ide of the m f the matr
P10O to P13 of the CPU (US01 pins 27 to 30) and the P10O to P13 of the CPU
other side is connected to Ports P14 to P17 (U501 pins other side is connected to Ports P14 to P17 (U501 pins
31 to 34). 31 to 34).
ditions are met (the RAM is he RAM is
RAM. . The The RAM RAM can
the 3478A's
(Write at U501 pin 10) is low.
tch brin rings on gs one inp e input o ut of NOR
the gate ate is a lo is a low fr w from t om the W
8C goes hi es high, a gh, and si nd since nce NOR
to receive new
Constants are
ery BT701 in the + 5V
should not
The RAM must be disabled. e disabled.
disabled by
The operation is as follows ollows
explanation):
8A is on, t on, the RA he RAM ge M gets it
, the RAM e RAM get gets its s its sup supply
diode CR764. The
data retention.
wer off, t ff, the RA he RAM is di M is disab sabled b
by comparator r
enses a low (or no + 5V) from + 5V) from
R763. Since U750OC's Since U750OC's
This makes line CE2 low and CE2 low and
tion. . The The Keyboard's Keyboard's
The operation is as
atrix is c ix is conn onnect ected to P ed to Port
(US01 pins 27 to 30) and the
b. b. Bef
low. When scanning begins, low.
port goes sequentially high. port goes sequentially high.
c. c. Dur
the CPU determines which one and if any of Ports P0O the CPU determines which one and if any of Ports P0O
to P13 are high. to P13 are high. A high on P10 to P13
can
determine the button pressed. determine the but
button is pressed and turns button is pressed and turns the corresponding SRQ
switch on. switch on. This connects Port
and
P11 high when P17 is high. Since the CPU knows when P11 high when P17 is high.
it sets P17 high and also knows when P 11 is high, the it sets P17 high and also knows when
pressed button is determined. pressed button is determined.
f NOR
7-F- 7-F-66. 66. Displa
alphanumeric display alphanumeric display with 12 annunc
sends serial data to the Display Circuitry which in turn sends serial data to the Display Circuitry which in turn
he WR R
does all the necessary decoding of the data (to display does all the necessary decoding of the data (to display
readings, etc.). ). The operation readings, etc.
NOR
a. a. Wit
data to the Display Circuitry. data to the Display
sent on the Data line (U506 pin 4). sent on the Data
Circuitry to receive and decode the data, the other Circuitry to receive and decode the data, the other
display lines have to send certain information to the display lines have to send certain information to the
are
circuitry. This is circuitry.
5V
inputs to receive data, I and 12. inputs to receive dat
from flip-flop U506 (pin3) and Port P25 for clock from flip-flop U506 (pin3) and Port P25 for clock
inputs 11 and inputs 11 and 12, respective
used as a latch between the CPU and used as a latch between the CPU and the Display
Circuitry.) Circuitry.)
instructions to the Display Circuitry. instructions to the Display Circuitry.
ts its s
the Display Circuitry when to look for instructions the
b. b. Wit
ply
US01 pin 36) low, the Display Circuitry operates without US01 pin 36) low, the Display Circuitry operates without
The
receiving any data f receiving any data from the CPU.
operate in this mode since it has an internal clock operate in this mode since it has an internal clock
(capacitor C502 is the frequency ref (capacitor C502 is t
led by y
circuitry in the internal mode, no updating of the display circuitry in the internal mode, no updating of the display
is done. Line PWO is is done.
7-F- 7-F-67. 67. HP-IB
CPU and the Hewl CPU and the Hewlett-Packard Interface Bus (HP-IB) is
done by the HP-IB Chip (U503) and two Bus done by the HP-IB Chip (U503) and two Bus
Transceivers (U50 Transceivers (U504 and USOS).
microprocessor and changes the data sent and microprocessor and changes the data sent and received
by the CPU to the necessary HP-IB information (e.g. by the CPU to the necessary HP-IB information (e.g.
Listen, Talk, etc.). ). The Transceivers tr Listen, Talk, etc.
is as
receive the HP-IB information between the HP-IB Chip receive the HP-IB information between the HP-IB
and the Bus. and the Bus. The circuitry
orts s
a. a. The HP-IB Ch
from the CPU's TO output (U501 pin 1). from the CPU's TO output (U501 pin 1).
7-F-19 7-F-19
Before s ore scan cannin ning sta g starts rts, Por
When scanning begins, starting with Port
During t ing the ti he time th me that th at the key
A high on P10 to P13 is used to
ton pressed. For example, the
the corresponding SRQ
This connects Port P11 to P17 and mak
Since the CPU knows when
Display Op y Operat eration ion. . The 3478A
with 12 annunciators.
The operation is as follows:
With lin h line PW e PWO hig O high, t h, the C
Circuitry. Data is in serial form
line (U506 pin 4). For the Display
This is as follows: as follows:
1. 1. The Di Th e Disp spla lay Ci y Circ rcui uitr try re
a, I and 12. The inputs come
12, respectively. ly. (Flip-flop U506
2. 2. The IS Th e ISA li A line ( ne (U5 U506 p
3. 3. The SY Th e SYNC l NC lin ine (U e (U50
Display Circuitry when to look for instructions. .
With lin h line PW e PWO (fr O (from P om Port
rom the CPU. The circuitry can
he frequency reference).
Line PWO is controlled by controlled by the CPU.
HP-IB Opera Operation tion. . All interfacing All interfacing between t
ett-Packard Interface Bus (HP-IB) is
4 and USOS). The HP-IB Chip
The Transceivers transfer and
The circuitry operates as operates as follows:
The HP-IB Chip (U503) rec ip (U503) receives its clock
TM 11-6625-3071-14 TM 11-6625-3071-14
, Ports P1 ts P14 to P1 4 to P17 are 7 are
starting with Port P14, each P14, each
e keyboa board is s rd is scan canned ned, ,
is used to
For example, the SRQ SRQ
P11 to P17 and makes es
P 11 is high, the
The 3478A Display is Display is an an
iators. The CPU The CPU
is as follows:
he CPU c PU can s an send end new new
Data is in serial form and is and is
For the Display
y requ quir ires t es two c wo cloc lock k
The inputs come
(Flip-flop U506 is is
the Display
06 pin 5 in 5) is ) is us used t ed to gi o give ve
506 pi 6 pin 6) n 6) is u is use sed to d to te tell ll
ort P23 o P23 of th f the CPU a e CPU at t
The circuitry can
erence). With the With the
the CPU.
between the he
The HP-IB Chip is a is a
received
ansfer and
Chip
follows:
eives its clock signal signal