HP 3478A Technical Manual page 116

3478A 3478A
comparators U468A and U468B. comparators U468A a nd U468B. The comparators
used to bring the low level output of T501 used to bring the low level output of T501 up to a TTL
level. level. The output of t The output of the comparators he comparators is applied to the TO
input of U462 (U462 pin 1), which is the same data as input of U462 (U462 pin 1), which is
the data sent by the data sent by US01. US01. This makes the out
of U501 the same as the input waveform of U462. of U501 the same as the input waveform of U462.
7-F-74. Serial data from 7-F-74. Serial data from U462 to U501 is sent
drivers U467A and U467B, transformer T401, and drivers U467A and U467B,
comparators USSOA and comparators USSOA and USSOB.
operation is the same as sending data from U501 to operation is the same as sending data from U501 to
U462 (see previous paragraph). U462 (see previous par
the data is input to the TI line the data is input to the TI line of USO1 (USO1 pin 39)
instead of TO, as is the case with U462. instead of TO, as is the case with
7-F 7-F-75 -75. . Flo Floati ating ng Com Common
7-F-76. 7-F-76. The main parts of The main parts of the Floating Common
Circuitry are the A/D Controller and the A/D Converter. Circuitry are the A/D Controller and the A/D Converter.
The A/D Controller consists of CPU U462 and the A/D The A/D Controller consists of CPU U462 and the A/D
Converter is Converter is U403 and associat U403 and associated circuitry.
circuitry includes an Digital to Analog Converter (U465 circuitry includes an Digital to Analog Converter (U465
and associated circuitry) and a and associated circuitry) and a Voltage Reference
Supply (U404, U405, and Supply (U404, U405, and U461).
the A/D Converter and Voltage Reference refer to the A/D Converter and Voltage
paragraph 7-F-49. The operation of t paragraph 7-F-49. The operation of the A/D Controller,
the Digital to Analog Converter, and other logic circuitry the Digital to Analog Converter, and other logic circuitry
is explained in the following paragraphs. is explained in the following paragraphs.
7-F-77 7-F -77. . A/D A/D Con Contro troller ller (U4
purpose of U462 is to control the A/D operation, set up purpose of U462 is to control the A/D operation, set up
the Digital to Analog Converter, and to send set-up the Digital to Analog Converter, and to send set-up
(Range and Function) information to the (Range and Function) information to the Input Hybrid
U102 (see paragraph 7-F-13 for its operation and U102 (see paragraph 7-F-13 for its operation and
purpose). purpose). The CPU also determines The CPU also determines measurement dat
from the A/D Converter and sends from the A/D Converter and sends the data (readings) to
the Chassis Common CPU (USO1). the Chassis Com mon CPU (USO1). The CPU (U462)
has an internal 128 bytes of RAM memory, 2K bytes of has an internal 128 bytes of RAM memory, 2K bytes of
ROM memory, and ROM memory, and a clock. a clock. The frequency and st
of the clock is determined by a 10.98MHz crystal Y460. of the clock is determined by a 10.98MHz crystal Y460.
The ROM is used to control the CPU operation and the The ROM is used to control the CPU
RAM is used to store Autozero constants (see paragraph RAM is used to store Autozero constants (see paragraph
7-F-14). Since the U462 has an 7-F-14). Since the U462 has an internal ROM, all
addressing and data transfer is done using bi-directional addressing and data transfer is done using bi-directional
Ports P10 to P17 (U462 pins 27 to Ports P10 to P17 (U462 pins 27 to 34) and P20 to P27
(U462 pins 27 to 34, 21 to 24, and 35 to 38). (U462 pins 27 to 34, 21 to 24,
7- 7-F- F-78 78. . A/D C A/ D Con onve vert rter er Co
receives control data from the CPU Ports P10O to P14 receives control data from the CPU Ports P10O to P14
(U462 pins 27 to 31). . The data is used t (U462 pins 27 to 31) The data is used to select the
various slopes (see paragraph 7-F-49) in the converter. various slopes (see paragraph 7-F-49) in
The output of the A/D Converter (CMP, the Comparator The output of the A/D Converter (CMP, the Comparator
Output) is applied to the Ti input of the CPU (at U462 pin Output) is applied to the Ti input of the CPU
1). The ALE output (Add 1). The ALE output (Address Latch Enable at
11) is used as the converter's clock. 11) is used as the converter's clock. Refer to paragra
7-F-31 for more information on the 7-F-31 for more information on the A/D operation.
7- 7-F- F-79 79. . In Inpu put t Hy Hybr brid id Co
Input Hybrid (U102) which come from Ports P15 to Input Hybrid (U102) which come from Ports P15 to
The comparators are
up to a TTL
is applied to the TO
the same data as
This makes the output waveform put waveform
U462 to U501 is sent using using
transformer T401, and
USSOB. The circuitry The circuitry
agraph). The difference is tha The difference is that t
of USO1 (USO1 pin 39)
U462.
mon Log Logic ic Cir Circui cuitry try
the Floating Common Logic
ed circuitry. Other Other
Voltage Reference
U461). For the explanation on For the explanation on
Reference refer to
he A/D Controller,
(U462) 62) Ope Operat ration ion. The . The
Input Hybrid
measurement data a
the data (readings) to
The CPU (U462)
The frequency and stability
operation and the
internal ROM, all
34) and P20 to P27
and 35 to 38).
Cont ntro rol l . . The A/ The A/D Conver D Converter
o select the
the converter.
(at U462 pin
ress Latch Enable at U462 pin U462 pin
Refer to paragraph
A/D operation.
Cont ntro rol l . . The contro The control lines to l lines to the
are
P17of the CPU and are: Data, Mode, P17of the CPU and a
lines do the following: lines do the following:
a. a. When the Clock input
data is transferred into the hybrid. data is transferred into the hybrid.
b. b. When the clock inpu
1. 1. When the Mode
on the Data line (U102 pin 26) is transferred into the on the Data line (U102 pin 26) i
hybrid (into an internal shift hybrid (into an internal shift register).
2. 2. When the Mode
hybrid (in its shift register) is used to set-up the switches hybrid (in its shift register) is used to set-up the switches
in the hybrid. in the hybrid.
7-F-80. 7-F-80. Digital to An
3478A's A/D Converter requires a 3478A's A/D Converter requires a certain offset voltage
Logic
(see paragraph 7-F-46 for more (see paragraph 7-
is applied to the negative input of the A/D Integrator is applied to the negative input of the A/D
(U401) and comes from the Digital to Analog Converter (U401) and comes from the Digital to Analog Converter
(DAC). (DAC). The offset voltage
R401 to R406, which are selected by Hex D flip-flop R401 to R406, which are selected by Hex D
U465. Each time the flip-f U465.
its QO to Q5 outputs are set either its QO to Q5 output
depends on the position (high or low) of Ports P20 to depends on the position (high or low) of Ports P20 to
P25. P25. The outputs in con The outputs in conjunction with resistors
R406 generates a certain offset voltage. R406 generates a certain offset voltage.
7- 7-F- F-81 81. .
CPU (US01) can reset the Floating Common CPU CPU (US01) can reset the Floating Common CPU
(U462) whenever needed. (U462) whenever
the 3478A is turned on. the 3478A is turned
a. a.
clocked by the ALE line (U462 pin 11). clocked by the ALE line (U462 pin
b. b.
bytes over the Isolation logic, the counter is reset each bytes over the Isolation logic, the counter is reset each
time the data byte has a high (a high resets the counter). time the data byte has a high (a high
ability
c. c.
high level from the data bytes), the counter keeps on high level from the data bytes), the counter keeps on
incrementing for about 11mS. incrementing for
then goes high. then goes high.
d. d.
U467C (connected like an inverter) and sets the CPU's U467C (connected like an inverter) and sets the CPU's
RESET line (U462 pin 14) low. RESET line (U462 pin 14) low. The CPU turns off
ter
e. e.
line receives a high from the data byt line receives a high fr
counter and its Q14 output goes low. counter and its Q14
the CPU goes high and U462 resets and turns on the CPU goes high and U462 resets and turns on to a
predefined condition. predefined condition.
7- 7-F- F-82 82. .
ph
Front/Rear Switch position is determined by Front/Rear Switch position is determined by the state
(high or low) of Po (high or low) of Port P26.
the
7-F-21 7-F-21
re: Data, Mode, and Clock.
When the Clock input (U102 pin 24) is low, no (U102 pin 24) is low, no
When the clock input is high, the following t is high, the following occurs:
When the Mode input (U102 pin 25) is input (U102 pin 25) is low, data
register).
When the Mode input is high, the dat input is high, the data in the
Digital to Analog Converter alog Converter Operation
F-46 for more information).
The offset voltages are developed by r s are developed by resistors
Each time the flip-flop is clocked by the AL lop is clocked by the ALE line,
s are set either high or low.
junction with resistors R401 to
CP CPU U Re Rese set t Op Oper erat ation ion. . The Chas
needed. This is normally This is normally done when
on. The operation is as The operation is as follows.
Coun Co unte ter U r U46 466 i 6 inc ncre reme ment nts e
As lo long As ng as as th the C e Cha hass ssis is Co
If If th the e co coun unte ter' r's s Re Rese set t lin
about 11mS. The counter's Q14 outp
Th The Q e Q14 14 ou outp tput ut is is in inve vert rted
The C Th e CPU PU re rema main ins o s off ff un
om the data bytes.
output goes low. The RESET line of
Fron Fr ont/ t/Re Rear Sw ar Swit itch Po ch Posi siti tion
rt P26. A low state is when t A low state is when the port is
TM 11-6625-3071-14 TM 11-6625-3071-14
and Clock. The The
occurs:
low, data
s transferred into the
a in the
Operation. The . The
certain offset voltage
information). This offset This offset
Integrator
esistors
flip-flop
E line,
high or low. This This
R401 to
The Chassis Com sis Common mon
done when
follows.
s eac ach t h tim ime i e it t is is
11).
Comm mmon on se send nds d s dat ata a
resets the counter).
line e st stay ays s low low (e (e.g .g. . no no
The counter's Q14 output ut
ed by by NO NOR g R gat ate e
The CPU turns off. .
unti til t l the he co coun unte ter' r's R s Res eset et
es. This resets the This resets the
The RESET line of
to a
on. . The The 3478A's 3478A's
the state
he port is