Memory - LG GD910 Service Manual

3.6 Memory

2Gbit NAND Flash & 1Gbit DDR SDRAM employed on GD910 with 16 bit parallel data bus thru ADD(0) ~
ADD(24). The 1Gbit Nand Flash memory with DDR SDRAM stacked device family offers multiple high-
performance solutions.
SD_ADD(0:13)
SD_ADD(0)
SD_ADD(1)
SD_ADD(2)
SD_ADD(3)
SD_ADD(4)
SD_ADD(5)
SD_ADD(6)
SD_ADD(7)
SD_ADD(8)
SD_ADD(9)
SD_ADD(10)
SD_ADD(11)
SD_ADD(12)
SD_DATA(0:15)
SD_ADD(13)
SD_DATA(0)
SD_DATA(1)
SD_DATA(2)
SD_DATA(3)
SD_DATA(4)
SD_DATA(5)
SD_DATA(6)
SD_DATA(7)
SD_DATA(8)
SD_DATA(9)
SD_DATA(10)
SD_DATA(11)
SD_DATA(12)
SD_DATA(13)
SD_DATA(14)
SD_DATA(15)
_BC0
_BC1
LDQS
UDQS
SDCLKI
SDCLKO
CKE
BA0
BA1
_RAS
_CAS
_WR
_RAM_CS
Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
Large Block Memory
(2048Mbit NAND / 1024 Mbit DDR SDRAM, 1.8V I/O)
D4
A0
E4
A1
F4
A2
G4
A3
G8
A4
F8
A5
E8
A6
D8
A7
D9
A8
G7
A9
G5
A10
F7
A11
E7
A12
E9
A13
L4
DQ0
M4
DQ1
N4
DQ2
L5
DQ3
M5
DQ4
N5
DQ5
M6 H8BCS0SI0MAP_56M
DQ6
N6
DQ7
M7
DQ8
N7
DQ9
L8
DQ10
M8
DQ11
N8
DQ12
L9
DQ13
M9
DQ14
N9
DQ15
K6
LDQM
K7
UDQM
L6
LDQS
L7
UDQS
C6
_CLK
C7
CLK
D7
CKE
E5
BA0
F5
BA1
BA1
F6
_RAS
E6
_CAS
D6
_WED
D5
_CS
[Figure 3.6-1] Memory circuit diagram
3. BB Circuit Technical brief
GD910 service manual
I_O10
I_O11
I_O12
I_O13
I_O14
I_O15
U100
_WEN
R__B
VCCN1
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSSQ
VDD1
VDD2
VDD3
VDDQ1
VDDQ2
- 39 -
NAND_IO(0:15)
NAND_IO(0)
P10
I_O0
NAND_IO(1)
N10
I_O1
NAND_IO(2)
M10
I_O2
NAND_IO(3)
L10
I_O3
NAND_IO(4)
F10
I_O4
E10 NAND_IO(5)
I_O5
D10 NAND_IO(6)
I_O6
C10
NAND_IO(7)
I_O7
N11 NAND_IO(8)
I_O8
M11
NAND_IO(9)
I_O9
L11 NAND_IO(10)
K11
NAND_IO(11)
G11 NAND_IO(12) 1V8_SD
F11 NAND_IO(13)
NAND_IO(14)
E11
D11 NAND_IO(15)
G3 _NAND_CS
_CE _NAND_CS
M3 _WR
_WR
F3 _RD
_RE _RD
L3
ALE SD_ADD(0)
K3
CLE SD_ADD(1)
E3
FCDP
N3
_WP _WP
H2
1V8_SD
C5
C9
G2
H10
P7
P9 1V8_SD
P5
C4
C8
P6
P4
P8
LGE Internal Use Only