JVC CA-MXS6MDR Service Manual page 59

HY51V17400CT-60 (IC390) : DRAM
1.Pin layout
Vcc
DQ0
DQ1
WE
RAS
A11
A10
A0
A1
A2
A3
Vcc
3.Block diagram
WE
CAS
Cloumn Predecoder
A0
A1
A2
A3
Refresh Counter
A4
A5
A6
A7
Refresh Counter
A8
A9
A10
*(A11)
Row Presecoder
RAS
2.Pin function
Pin Name
Vss
/RAS
DQ3
/CAS
DQ2
CAS
/WE
OE
/OE
A9
A0~A11
A8
A0~A10
A7
A6
DQ0~DQ3
A5
Vcc
A4
Vss
Vss
NC
CAS Clock
Generator
(11/12)*
(11/12)*
(11/12)*
RAS Clock
Generator
X16 Parallel
Test
Row Address Strobe
Column Address Strobe
Write Enable
Output Enable
Address Input (4K Refresh Product)
Address Input (2K Refresh Product)
Data In/Out
Power (3.3V)
Ground
No Connection
DQ0 DQ1 DQ2 DQ3
4
Data Input Buffer Data Output Buffer
DQ0~3
4
(11/10)*
Column Decoder
Sense Amp
Row
Memory Array
Decoder
4,194,304 x 4
Substrate Bias
CA-MXS6MDR
SP-MXS6MD
Parameter
4
OE
DQ0~3
4
I/O Gate
Vcc
Generator
Vss
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