Control Register - Epson RA8804 CE Applications Manual

RA8804 CE

8.2.7. Control register

Address
Control Register
0F
1. The default value is the value that is read (or is set internally) after powering up from 0 V.
"o" indicates write-protected bits. A zero is always read from these bits.
2.

This register is used to control interrupt event output from the /INT pin and the stop/start status of clock
and calendar operations.
1) CSEL0, 1 (Compensation interval Select 0, 1) bits
The combination of these two bits is used to set the temperature compensation interval.
Write/Read
2) UIE (Update Interrupt Enable) bit
When a time update interrupt event is generated (when the UF bit value changes from 0 to 1), this bit's value
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status
remains Hi-Z).
When a "1"is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an
interrupt event is generated.
When a "0"is written to this bit, no interrupt signal is generated when an interrupt event occurs.
UIE Data
Write/Read
3) TIE (Timer Interrupt Enable) bit
When a fixed-cycle timer interrupt event occurs (when the TF bit value changes from "0" to "1"), this bit's value
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status
remains Hi-Z).
When a "1"is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an
interrupt event is generated.
When a "0"is written to this bit, no interrupt signal is generated when an interrupt event occurs.
TIE Data
Write/Read
Function bit 7
CSEL1
(Default) (0)
CSEL1
CSEL0,1
(bit 7)
0
0
1
1
When a time update interrupt event occurs, an interrupt signal is not generated
0
or is canceled (/INT status changes from low to Hi-Z).
When a time update interrupt event occurs, an interrupt signal is generated
(/INT status changes from Hi-Z to low).
1 
When a time update interrupt event occurs, low-level output from the /INTpin occurs only when
the value of the control register's UIE bit is "1". This /INT status is automatically cleared (/INT
status changes from low to Hi-Z) earliest 7.813ms after the interrupt occurs.
When a fixed-cycle timer interrupt event occurs, an interrupt signal is not
0
generated or is canceled (/INT status changes from low to Hi-Z).
When a fixed-cycle timer interrupt event occurs, an interrupt signal is
generated (/INT status changes from Hi-Z to low).
1
*
When a fixed-cycle timer interrupt event has been generated low-level output from the /INT pin
occurs only when the value of the control register's TIE bit is 1. Earliest 7.813 ms after the interrupt
occurs, the /INT status is automatically cleared (/INT status changes from low to Hi-Z)
bit 6 bit 5 bit 4
CSEL0 UIE TIE
(1) (0) (0)
CSEL0
(bit 6) Compensation interval
0 0.5 s
Default
1 2.0 s
0 10 s
1 30 s
Function
Function
Page - 13
bit 3 bit 2 bit 1
 
AIE
(0) (0) (0)
.
ETM60E-02
bit 0
RESET
(0)