Related Registers For Function Of Fixed-Cycle Timer Interruption; Timer Register - Epson RA8804 CE Applications Manual

RA8804 CE

8.3.2. Related registers for function of fixed-cycle timer interruption

The fixed-cycle timer interrupt generation function generates an interrupt event periodically at any fixed cycle set
between 244.14 s and 16777215 minutes.
Address Function
0B Timer Counter 0
0C Timer Counter 1
0D Extension Register
0E Flag Register
0F Control Register
1B Setup of Timer
1C Monitor of Timer 0
1D Monitor of Timer 1
1E Monitor of Timer 2
1F Timer Counter 2

Timer Counter 0, 1, 2 are preset value of Timer.

Monitor of Timer 0, 1, 2 are current count value of a timer.

Before entering settings for operations, we recommend writing a "0" to the TE and TIE bits to prevent
hardware interrupts from occurring inadvertently while entering settings.

When the RESET bit value is "1" the time update interrupt function does not operate.

When the fixed-cycle timer interrupt function is not using, the fixed-cycle timer counter (0Bh, 0Ch,1Fh),
these can use as a RAM register. In such cases, stop the fixed-cycle timer function by writing "0" to the
TE and TIE bits.

When writes 00h to all timer counter, Timer countdown are stop, and new Timer interruption are
inhibited.
1) TSEL0, 1 (Timer Select 0, 1) bits
The combination of these two bits is used to set the countdown period (source clock) for the fixed-cycle timer
interrupt function (four settings can be made).
TSEL0,1
Write/Read
1. tRTN is different with a source clock in automatic release time. TF is not cleared automatically.
2. Source clock of 1Hz does not synchronize to update of a second. (It is a 1Hz clock for timers)
3. Source clock 1/60Hz synchronize in update of a minute.
4. A preset value, it is loaded with the first source clock of a timer counter after having set TE.
5. Therefore, two periods of source clocks are needed at the maximum till the first countdown starts after
TE="1".
TE
Source Clock
Down counter
Preset Value
TF
When timer count value is 0 from 1, preset value is loaded at the same time by a
timer. Therefore, can't monitor 0 of timer counter.
Delay of the first countdown. Preset value is 3.
bit 7 bit 6 bit 5
128 64
32768 16384 8192
TEST WADA USEL
 
CSEL1 CSEL0 UIE
TSTP TRES
128 64
32768 16384
8388608 4194304 2097152
8388608 4194304 2097152
TSEL1 TSEL0
(bit 1) (bit 0)
0 0
0 1 *Default 64 Hz / Once per 15.625ms
Second" update / Once per second
1 0
"Minute" update / Once per minute
1 1
Period of Clock
Delay
undefine 3
3
Load preset value
bit 4 bit 3
32 16 8
4096 2048
TE FSEL1
UF TF AF
TIE AIE
  
32 16 8
8192 4096 2048
1048576 524288
1048576 524288
Source clock
4096 Hz / Once per 244.14 µs
2
Page - 16
bit 2 bit 1 bit 0
4 2 1
1024 512 256
FSEL0 TSEL1 TSEL0

VLF VDET
 
RESET
  
4 2 1
1024 512 256
262144 131072 65536
262144 131072 65536
Auto reset time
tRTN (Min.)
122 µs
7.813ms
7.813ms
7.813ms
1 3
TF "0" ⇒ "1"
Read Write
 
 
 

Clear only
 
 

-

-

-
 
Effects of
RESET bits


Does not operate
when the RESET
bit value is "1".
ETM60E-02