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Sharp UP-5900 Service Manual

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CHAPTER 1. SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 1
CHAPTER 2. OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 1
CHAPTER 3. SERVICE PRECAUTION . . . . . . . . . . . . . . . . . . . . . 3 - 1
CHAPTER 4. DIAGNOSTICS SPECIFICATIONS . . . . . . . . . . . . . 4 - 1
CHAPTER 5. CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 5 - 1
CHAPTER 6. BIOS SETUP UTILITY . . . . . . . . . . . . . . . . . . . . . . . 6 - 1
CHAPTER 7. HDI RECOVERY PROCEDURES . . . . . . . . . . . . . . 7 - 1
CHAPTER 8. ABOUT UTILITY SOFTWARE . . . . . . . . . . . . . . . . . 8 - 1
CHAPTER 9. CIRCUIT DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 1
CHAPTER 10. PWB LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 1
PARTS GUIDE
Parts marked with "!" are important for maintaining the safety of the set. Be sure to replace these parts with specified
ones for maintaining the safety and performance of the set.
SERVICE MANUAL
CONTENTS
SHARP CORPORATION
CODE : 00Z
POS TERMINAL
UP-5900
MODEL
("V/VK" version)
This document has been published to be used
for after sales service only.
The contents are subject to change without notice.
UP5900VSME

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Summary of Contents for Sharp UP-5900

  • Page 1: Table Of Contents

    SERVICE MANUAL CODE : 00Z UP5900VSME POS TERMINAL UP-5900 MODEL ("V/VK" version) CONTENTS CHAPTER 1. SPECIFICATIONS ......1 - 1 CHAPTER 2.
  • Page 2 BATTERY DISPOSAL Contains Nickel Metal Hydride Battery. Must be Disposed of Properly. Contact Local Environmental Officials for Disposal Instructions. CAUTION RISK OF EXPLOSION IF BATTERY IS REPLACED BY AN INCORRECT TYPE. DISPOSE OF USED BATTERIES ACCORDING TO THE INSTRUCTIONS. AVOID: SHORT-CIRCUITING THE BATTERY TERMINALS. KEEP THE BATTERY AWAY FROM FIRE.

  • Page 3: Chapter 1. Specifications

    Set the power switch to the ON ( I ) position after the terminal has been When the LCD display can no longer be adjusted and becomes darker, plugged in. you should replace the LCD module. Consult your authorized SHARP dealer for further details. Power indicator When the power switch is turned on, the power indicator will light up.
  • Page 4 Clear to Send (Changing key layout by using ER-11KT7/12KT7/22KT7) 3-5. EXPANSION SLOT Key layout 5V PCI board can built in UP-5900 instead of an ISA PC board. It has to satisfy with power consumption as follows. ITEM SPECIFICATION NOTE Type...
  • Page 5 Use this switch only when the main power source is not cut off [JUMPER SWITCH] even if the main unit power switch is set to OFF position. The UP-5900 JP1: Setting of IRQ allocated to COM3. is turned OFF and the hardware is reset by turning the main power...

  • Page 6: Chapter 2. Options

    CHAPTER 2. OPTIONS 1. SYSTEM CONFIGURATION Incorporated in Main Unit In-line Communication Connection (Ethernet) Host UP-5900 POS terminal RS-232 Communication Connection (RS-232) max.3 PC server <Local item> Additional DRAM Memory <Local item> Remote Printer Magnetic <Local item> Card Reader <Option>...
  • Page 7 *1 Extension RAM module 4. SERVICE OPTIONS [Device] 168pin DIMM NAME PARTS CODE PRICE DESCRIPTION [Outline] UP-5900 has a socket as DIMM. The following DIMM memory specification must be adhered QCNW-7858BHZZ 1 Connector cable Relay line from for Dongle Terminal to Dongle...
  • Page 8 NAME PARTS CODE PRICE DESCRIPTION NAME PARTS CODE PRICE DESCRIPTION LKGIM1004BH50 LKGIM1004BH00 Key No.50 Key No.100 LKGIM1004BH51 LKGIM1004BHA1 Key No.51 Key No.101 LKGIM1004BH52 LKGIM1004BHA2 Key No.52 Key No.102 LKGIM1004BH53 LKGIM1004BHA3 Key No.53 Key No.103 LKGIM1004BH54 LKGIM1004BHA4 Key No.54 Key No.104 LKGIM1004BH55 LKGIM1004BHA5 Key No.55...
  • Page 9 Connected to the RS232 connector (D-SUB 9 pin: COM1, COM2) of the the parallel port through the Dongle cable (QCNW-7858BHZZ) for UP-5900 and ER-A8RS, and used to check loop signals when execut- checking the parallel port during execution of diagnostics.

  • Page 10: Chapter 3. Service Precaution

    If water or oil is put around the air groove, it may penetrate inside. Be careful to keep the air groove away from water and oil. • Do not use sharp objects when making input entrees. UP-5900VS SERVICE PRECAUTION 3 – 1...
  • Page 11 Add the core to the AC cord GND The UP-5900 can be externally connected to a keyboard. wire for increasing the EMI margin. The UP-5900’s key BIOS conforms to the PC standard, but this BIOS’s Core added: SC18B (RCORF6698BHZZ) operation is not compatible for some keyboards.
  • Page 12 ■ ■ ■ ■ LCD cable treatment Binding position of the binding band Binding band Binding band BNF18 Inside Fig.1 LCD cable treatment and core addition The binding position of the band must be inside of this position. Procedure 3 Procedure 1 Pass the binding band through the core as shown in the photo.
  • Page 13 This diagnostic program is used to check the PWB’s, the process, and 3-13. System Switch Diagnostics ..........4-9 the machine of the UP-5900 series in a simplified manner. 1) System Switch............4-9 This test program is supplied with floppy disks.

  • Page 14: Service Diagnostics

    End” and press the Enter key to terminate the diagnostics. For the extended memory test, the value is set in the setup of the read test and is made to the area in increments of 512KB. SHARP PC-POS System Diagnostic Series Version 1.00A 2 Display...

  • Page 15: Rom Diagnostics

    3-4. ROM DIAGNOSTICS 2) CMOS RAM CHECK 1 Checking content The BIOS ROM, is tested. The read/write check is performed for the CMOS-RAM when setting 1) BIOS ROM CHECK up. The checking procedure is as follows: 1 Checking content Test address data is saved to the main memory. The BIOS ROM version is displayed.

  • Page 16: Touch Panel Diagnostics

    2 Content 2 Display When a key is pressed, its color changes and the key catch sound is Controller Diag Test made. Pass!! ROM Error!! Error!! The keys to be checked and their positions are as shown below. RAM Error!! Error!! PANEL Voltage Error!! Back...

  • Page 17: Clerk Key Diagnostics

    3-8. CLERK KEY DIAGNOSTICS 1) PARALLEL LOOP BACK CHECK (European model only) 1 Checking content The clerk key input test is performed. To check the parallel port DSub 25 pin, use the connector (UKOG- 2366BHZZ) for Parallel Loop Back Test. Pressing the Esc key returns to the serviceman diagnostics menu.

  • Page 18: Serial I/O Diagnostics

    7pin 8pin Loop back connector (UKOG-6729BHZZ) wiring diagram The UP-5900’s 9-pin D-sub ports are used as COM1 and 2. The UP- 5900 also provides a RJ45 port is used as COM3. The following menu is displayed. The highlighted cursor is moved by the cursor keys (UP 2 and DOWN 4 ) of the PS2 keyboard.

  • Page 19: Com1 Check

    3E8H. UART setting is made. If access is denied to UART at that time, When the RJ-45 port of the UP-5900 main unit is assigned to “COM1 Disabled” is displayed and the following check is not COM3, the following points are different from COM1 Check : performed.
  • Page 20 iv. Reversed pattern of pattern iii. ix. All white pattern x. Color bar (16 colors) Color bars of 16 colors are displayed. v. Horizontal stripe pattern in 1 dot interval xi. Color pattern (256 colors) Color pattern of 256 colors is displayed. The displayed colors are the default pallet.

  • Page 21: Magnetic Card Reader Diagnostics

    2 Display Esc key returns to the service diagnostics menu. MCR (Magnetic Card Reader) Check Drawer Diagnostics TRACK1: SHARP TEST CARD 0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789 UKOG-6718RCZZ Drawer 1 Check Drawer 2 Check TRACK2: 0123456789012345678901234567 The above display is made when the card (UKOG6718RCZZ) is passed through the MCR.

  • Page 22: Drawer 1 Check

    1) DRAWER 1 CHECK ii. The test pattern with all digits ON is displayed. 1 Checking content The drawer 1 solenoid is turned on and the drawer open sensor value is sensed at every 100ms and the state is displayed. When Drawer 1 and Drawer 2 are connected, “CLOSE”...

  • Page 23: [Read Mode Test]

    2 Display [READ MODE TEST] Sequential Seek test execution screen 1) DRIVE STATUS DISPLAY 1 Checking content Sequential Seek test @Cylinder range ? Error Kinds The hard disk drive standard values (Memory capacity, Number of [000 XXX] = 000-XXX Drive not ready XXXX (XXX is displayed by checking the Bad controller XXXX cylinders.

  • Page 24: Seek & Read Test

    2 Display 4) SEEK & READ TEST [Test condition setting] Seek & Read test Same as the above sequential read. The following setting is additionally @Cylinder range ? Error Kinds [000 XXX] = 000-XXX required. Drive not ready XXXX (XXX is displayed by checking the Bad controller XXXX inmost cylinder.) •...

  • Page 25: Hd Dump Test

    2 Display 2 Display HD Dump test Target Sector Read test @Physical address ? [CCC. HH. SS] = 000. 00. 01 @Cylinder range ? Error Kinds The first hslf sector [000 XXX] = 000-XXX Drive not ready XXXX 000 : HHHH..HHHH-HHHH..HHHH : AAA..AA (XXX is displayed by checking the Bad controller XXXX (100)

  • Page 26: Controller Check Test

    Press the space key to resume the test. The correct password is “sharp” or “SHARP” in 5 digits. When typing When the “Continue” is set, even if an error occurs, the error display the correct password, the “...

  • Page 27: Target Sector Write/Read-Verify Test

    10) TARGET SECTOR WRITE/READ-VERIFY TEST 12) ERROR LOGGING AREA CLEAR 1 Checking content [Test conditions setting] Similar to test 5). Cylinder range setting is 000 *0* (Final cylinder 2). The last cylinder area in the HD is cleared with 00H. 1 Checking content (Error logging area: last cylinder, all sectors of 0 head) The areas to be cleared with 00H is the last cylinder and all the sec-...

  • Page 28: Error Information Storing Area Description

    16) ERROR INFORMATION STORING AREA Note: An error message appears at the hatched area 1 Error information storing area for diagnostics Error message Description Drive not ready No FD in drive 1 sector ~ 6 sector of 0 head of the last cylinder is used. Verify error Write data is different from Read data Used in the following format from the head of each sector.

  • Page 29: Operating Procedure Of Lan Interface Diagnostics

    *Do not load any device drivers when using this program. played. *To operate other applications after performing this program, re-boot IN the UP-5900, the seal indicating the lower 6 digits (08 00 1F) of the machine. the MAC address is attached to the position shown in the figure below on the main PWB.
  • Page 30 Fig. 5 Fig. 7 In Diagnostics On Network, one unit of the UP-5900 is set as the initia- tor and the other as the responder. To execute the program, execute "Set Up As Responder" on the main menu of the responder unit before executing "Set up As Initiator"...

  • Page 31: Chapter 5. Circuit Description

    LPT1 Customer Display UP-I20DP 2 line 20 digits dot display (5) POS System Controller <SHARP: PSC2 (LZ9AM22)> Mounted in the cabinet Customer Pole Display UP-P20DP 2 line 20 digits dot display BIOS ROM Bank Control: Fixed 2 banks...
  • Page 32 2. BLOCK DIAGRAM CPU Power Clock Generator Socket 370 GTL+ 168pin DIMM North Bridge VGAC 440BX DIMM 128Mbyte Lynx3DM4+ LVDS AGP bus Analog PCI bus Touch RJ-45 Panel LANC RTL8139C SLOT South Bridge Controller PIIX4e Port 8MHz ISA bus 7.37MHz PSC2 I SA Clerk SW...
  • Page 33 3. MEMORY MAP MainMemory (System) 0000000 SDRAM BIOS Memory Standard 128MB A0000 VGA RAM 128MB C0000 VGA BIOS 40kB C9FFF 144kB A000000 SDRAM Option 128MB (Max) F0000 System BIOS 64kB FFFFF 4. I/O ADDRESS MAP 4-1. PC SPECIFICATION Address Standard I/O [Option I/O] Address Legacy ISA I/O 00-0F...
  • Page 34 Address Standard I/O [Option I/O] Address Legacy ISA I/O C0-DE DMA ch4-7 control [PnP ISA Auto Configuration Port] F0-F1 (Coprocessor busy clear/reset) A7A-BFF 65550 (VGAC) Global Enable Register C00-CF7 CF8-CFF PCI Configuration 110-16F D00-D7F 170-177 Secondary IDE control D80-D9F Reserved[POS I/O] 180-19F POS I/O DA0-FFF...
  • Page 35 6. INTERRUPT 6-1. IRQ MAPPING Master 8259 Slave 8259 Fixed ISA Default Power On Default Available Device UP-5900 Recommended IRQ0 System timer Timer Timer Timer IRQ1 Keyboard IRQ2 PIC cascade (Cascade) (Cascade) IRQ8 RTC/CMOS RTC/CMOS RTC/COMS RTC/CMOS IRQ9 — IRQx...
  • Page 36 6-2. IRQ BLOCK CHART = No Mount South PSC2 IRQ9 PIRQ9 IRQ9 2.7K IRQ15 PIRQ15 IRQ15 2.7K IRQ3 PIRQ3 IRQ3 IRQ4 PIRQ4 IRQ4 2.7K IRQ10 PIRQ10 IRQ10 PIRQ11 IRQ11 IRQ11 Ultra I/O IRQ10 IRQ11 IRQ3 IRQ4 IRQ5 IRQ5 IRQ6 IRQ6 IRQ7 IRQ7 IRQ12...
  • Page 37 (Not Used) Device 3 REQ3#, GNT3# PCI Slot 8. SM BUS Address Device Remark 10100000b DIMM 0 UP-5900 standard memory supports SPD. 10100010b DIMM 1 DIMM can be set with SPD. 00110000b LM84CIM CPU Temperature SENSOR 11010010b ICS9248 Clock Generator 9.
  • Page 38 9-1. PIN ASSIGNMENTS 11 12 14 15 24 25 31 32 34 35 V S S A 1 2 A 1 6 R S V R S V R S V B P R I D E F E R R S V R S V T R D Y...
  • Page 39 Signal Type Description BSEL[1:0] I/O These signals are used to select the system bus frequency. The frequency is determined by the processor(s), chipset, and frequency synthesizer capabilities. All system bus agents must operate at the same frequency Individual proces- sors will only operate at their specified front side bus (FSB) frequency. On motherboards which support operation at either 66 MHz or 100 MHz, a BSEL[1:0] = “x1”...
  • Page 40 Signal Type Description INIT# The INIT# (Initialization) signal, when asserted, resets integer registers inside all processors without affecting their internal (L1) caches or floating-point registers. Each processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion.
  • Page 41 Signal Type Description SLOTOCC# SLOTOCC# is defined to allow a system design to detect the presence of a terminator card or processor in a SC242 (S.E.P.P. only) connector. This pin is not a signal; rather, it is a short to VSS. Combined with the VID combination of VID[4:0]= 11111 , a system can determine if a SC242 connector is occupied, and whether a processor core is present.
  • Page 42 10. CHIPSET (NORTH BRIDGE) Intel’s 82443BX is used. 10-1. PIN ASSIGHMENTS HD33# HD31# HD27# HD19# HD20# HD10# HD6# HD3# HA29# HA24# HA22# AD20 PCIRST# AD25 AD29 PREQ0# HD56# HD62# HD55# HD54# HD49# HD47# HD40# HD43# HD32# HD29# HD25# HD21# HD18# HD12# HD8# HD0#...
  • Page 43 Name Type Description HITM# Hit Modified: Indicates that a caching agent holds a modified version of the requested line and that this agent assumes GTL+ responsibility for providing the line. Also driven in conjunction with HIT# to extend the snoop window. HLOCK# Host Lock: All CPU bus cycles sampled with the assertion of HLOCK# and ADS#, until the negation of HLOCK# must GTL+...
  • Page 44 Name Type Description GCKE/CKE1 Global CKE (SDRAM): Global CKE is used in a 4 DIMM configuration requiring power down mode for the SDRAM. CMOS External logic must be used to implement this function. SDRAM Clock Enable (CKE1): In mobile mode, SDRAM Clock Enable is used to signal a self-refresh or power-down command to an SDRAM array when entering system suspend.
  • Page 45 Name Type Description Parity: PAR is driven by the 82443BX when it acts as a PCI initiator during address and data phases for a write cycle, and during the address phase for a read cycle. PAR is driven by the 82443BX when it acts as a PCI target during each data phase of a PCI memory read cycle.
  • Page 46 ■ ■ ■ ■ AGP Interface Signals Name Type Description AGP Sideband Addressing Signals PIPE# Pipelined Read: This signal is asserted by the current master to indicate a full width address is to be queued by the target. The master queues one request each rising clock edge while PIPE# is asserted. When PIPE# is deasserted no new requests are queued across the AD bus.
  • Page 47 Note: 1. AGP Sideband Addressing Signals. The above table contains two mechanisms to queue requests by the AGP master. Note that the master can only use one mechanism. When PIPE# is used to queue addresses the master is not allowed to queue addresses using the SBA bus. For exam- ple, during configuration time, if the master indicates that it can use either mechanism, the configuration software will indicate which mechanism the master will use.
  • Page 48 11. CHIPSET (SOUTH BRIDGE) Intel’s PIIX4E is used. 11-1. PIN ASSIGHMENTS PCIR- AD27 IDSEL AD19 FRA- SERR# AD13 AD1 PCIR- PHLD- SDD6 SDD4 SDD13 SDDR- SDD- SDA2 PDD8 PDD7 ME # EQB# ACK# AD31 AD26 AD23 AD18 IRDY# PAR AD12 AD0 PCIR- PHO- SDD9 SDD-...
  • Page 49 Name Type Description IDSEL INITIALIZATION DEVICE SELECT. IDSEL is used as a chip select during PCI configuration read and write cycles. PIIX4E samples IDSEL during the address phase of a transaction. If IDSEL is sampled active, and the bus com- mand is a configuration read or write, PIIX4E responds by asserting DEVSEL# on the next cycle.
  • Page 50 Name Type Description IOCHRDY I/O CHANNEL READY. Resources on the ISA Bus negate IOCHRDY to indicate that wait states are required to complete the cycle. This signal is normally high. IOCHRDY is an input when PIIX4E owns the ISA Bus and the CPU or a PCI agent is accessing an ISA slave, or dur- ing DMA transfers.
  • Page 51 Name Type Description SMEMR# STANDARD MEMORY READ. PIIX4E asserts SMEMR# to request an ISA memory slave to drive data onto the data lines. If the access is below the 1-Mbyte range (00000000h 000FFFFFh) during DMA compatible, PIIX4E mas- ter, or ISA master cycles, PIIX4E asserts SMEMR#. SMEMR# is a delayed version of MEMR#. During Reset: High-Z After Reset: High During POS: High...
  • Page 52 ■ ■ ■ ■ DMA SIGNALS Name Type Description DACK[0,1,2,3]# DMA ACKNOWLEDGE. The DACK# output lines indicate that a request for DMA service has been granted by PIIX4E or that a 16-bit master has been granted the bus. The active level (high or low) is programmed via the DMA DACK[5,6,7]# Command Register.
  • Page 53 Name Type Description IRQ 12/M INTERRUPT REQUEST 12. In addition to providing the standard interrupt function as described in the pin descrip- tion for IRQ[3:7,9:11,14:15], this pin can also be programmed to provide the mouse interrupt function. When the mouse interrupt function is selected, a low to high transition on this signal is latched by PIIX4E and an INTR is generated to the CPU as IRQ12.
  • Page 54 Name Type Description SMI# SYSTEM MANAGEMENT INTERRUPT. SMI# is an active low synchronous output that is asserted by PIIX4E in response to one of many enabled hardware or software events. The CPU recognizes the falling edge of SMI# as the highest priority interrupt in the system, with the exception of INIT, CPURST, and FLUSH.
  • Page 55 Name Type Description PDDREQ PRIMARY DISK DMA REQUEST. This input signal is directly driven from the IDE device DMARQ signal. It is asserted by the IDE device to request a data transfer, and used in conjunction with the PCI bus master IDE function. It is not associated with any AT compatible DMA channel.
  • Page 56 Name Type Description SDDACK# SECONDARY DMA ACKNOWLEDGE. This signal directly drives the IDE device DMACK# signal. It is asserted by PIIX4E to indicate to IDE DMA slave devices that a given data transfer cycle (assertion of SDIOR# or SDIOW#) is a DMA data transfer cycle.
  • Page 57 ■ ■ ■ ■ POWER MANAGEMENT SIGNALS Name Type Description BATLOW#/ BATTERY LOW. Indicates that battery power is low. PIIX4E can be programmed to prevent a resume operation GPI9 when the BATLOW# signal is asserted. If the Battery Low function is not needed, this pin can be used as a general- purpose input. CPU_STP#/ CPU CLOCK STOP.
  • Page 58 ■ ■ ■ ■ GENERAL PURPOSE INPUT AND OUTPUT SIGNALS Some of the General Purpose Input and Output signals are multiplexed with other PIIX4E signals. The usage is determined by the system configura- tion. The default pin usage is shown in Table 1 and Table 2. The configuration can be selected via the General Configuration register and X-Bus Chip Select register.
  • Page 59 Control Register and Bit Signal Name Multiplexed With Default Notes (PCI Function 1) GPO15 SUSB# SUSB# GENCFG Not available as GPO if using for power management. Bit 17 GPO16 SUSC# SUSC# GENCFG Not available as GPO if using for power management. Bit 17 GPO17 CPU_STP#...
  • Page 60 ■ ■ ■ ■ POWER AND GROUND PINS Name Type Description CORE VOLTAGE SUPPLY. These pins are the primary voltage supply for the PIIX4E core and IO periphery and must be tied to 3.3V. VCC (RTC) RTC WELL VOLTAGE SUPPLY. This pin is the supply voltage for the RTC logic and must be tied to 3.3V. VCC (SUS) SUSPEND WELL VOLTAGE SUPPLY.
  • Page 61 13. PS/2 KEYBOARD CONTROLLER M38813 of Mitsubishi Electric is employed to control the keyboard and the mouse. In the UP-5900, IRQ12 is not used and therefore no mouse can be use. 13-1. PIN ASSIGNMENT Name Default Signal Name Default Signal...
  • Page 62 14. VIDEO SUB-SYSTEM Silicon Motion's Graphic Controller (SM722G4) is used to allow control of the LCD Panel (1024 u 768 u RGB TFT). Signals are outputted at LVDS. 14-1. PIN ASSIGNMENTS Host Interface is of AGP Bus connection. Graphic Memory includes SGRAM of 4Mbyte in 256K u 32-bit u 4 composition. MD12 MD4 MD5 MD7 MD31 MD17 MD28 MD20 MD25 MD22 AD0 AD4 AD7 AD9 AD12 AD14 PAR...
  • Page 63 14-2. PIN DESCRIPTION 'HVFULSWLRQ 6LJQDO 1DPH 7\SH 3XOOXS 3XOO'RZQ +RVW ,QWHUIDFH 3&, RU $*3 0XOWLSOH[HG $GGUHVV DQG 'DWD %XV $ EXV WUDQVDFWLRQ $' >@ FRQVLVWV RI DQ DGGUHVV F\FOH IROORZHG E\ RQH RU PRUH GDWD F\FOHV %XV &RPPDQG DQG %\WH (QDEOHV 7KHVH VLJQDOV FDUU\ WKH & EXV FRPPDQG GXULQJ WKH DGGUHVV F\FOH DQG E\WH HQDEOH a%( >@...
  • Page 64 6LJQDO 1DPH 7\SH 3XOOXS 'HVFULSWLRQ 3XOO'RZQ a3'2:1 SXOOXS 3RZHU GRZQ PRGH HQDEOH a&/.581 SXOOXS a&/.581 RU $&7,9,7< /\Q['0 0HPRU\ DQG ,2 DFWLYLW\ GHWHFWLRQ GHSHQGLQJ RQ 6&5 >@ VHOHFW a&/.581 VHOHFW $&7,9,7< &ORFN ,QWHUIDFH 5()&/. SXOOXS .+] UHIUHVK FORFN VRXUFH IRU SRZHU GRZQ 3$/&/.
  • Page 65 6LJQDO 1DPH 7\SH 3XOOXS 'HVFULSWLRQ 3XOO'RZQ )ODW 3DQHO ,QWHUIDFH )'$7$ >@ SXOOGRZQ )ODW 3DQHO 'DWD %LW  WR %LW  IRU VLQJOH SDQHO LPSOHPHQWDWLRQ /3)+6<1& SXOOGRZQ '671 /&' /LQH 3XOVH 7)7 /&' /&' +RUL]RQWDO 6\QF )3)96<1& SXOOGRZQ '671 /&' )UDPH 3XOVH 7)7 /&' /&' YHUWLFDO V\QF 0'( SXOOGRZQ...
  • Page 66 6LJQDO 1DPH 7\SH 3XOOXS 'HVFULSWLRQ 3XOO'RZQ 3 >@ SXOOGRZQ 5*% RU <89 LQSXW 5*% GLJLWDO RXWSXW 3&/. SXOOXS 3L[HO &ORFN 95() SXOOXS 96<1& LQSXW IURP 3& &DUG RU YLGHR GHFRGHU +5() SXOOXS +6<1& LQSXW IURP 3& &DUG RU YLGHR GHFRGHU %/$1.
  • Page 67 The current flowing through the CCFL can be varied by controlling the current flowing between REF and ICCFL pin of the LT1184. In the UP-5900, VR1 on the main PWB is operated to change the current flowing between REF and ICCFL pin, controlling the current flowing through the CCFL and adjusting the brightness.
  • Page 68 16. ULTRA I/O National semiconductor’s PC87309 is used. 16-1. PIN ASSIGNMENT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 WDATA CTS1 DR1/DENSEL...
  • Page 69 Signal/Pin I/O and Pin Number Module Function Name Group # BUSY Parallel Port Input Busy – This pin is set high by the printer when it cannot accept another character. It is Group 2 internally connected to a weak pull-down resistor. This signal is multiplexed with WAIT.
  • Page 70 Signal/Pin I/O and Pin Number Module Function Name Group # UART2 Input Identification – These ID signals identify the infrared transceiver for Plug and Play sup- Group 1 port. These pins are read after reset. ID0,1,2 are multiplexed implicitly with IRSL0,1,2 respectively by the UART2 cell. ID3 is multiplexed with SIN2.
  • Page 71 Signal/Pin I/O and Pin Number Module Function Name Group # PD7-0 82-75 Parallel Port Parallel Port Data – These bidirectional signals transfer data to and from the peripheral Group 9 data bus and the appropriate parallel port data register. These signals have a high cur- rent drive capability.
  • Page 72 17. POS SYSTEM CONTROLLER 2 17-2. MEMORY CONTROL (NOT USED) This is connected to ISA bus by using Sharp's LZ9AM22, and used to 17-3. I/O CONTROL control POS devices. (1) Special System Register Special System Register 1: 07F1h The special system register has a input port reading setup data defin-...
  • Page 73 (3) RS232 Interface (6) Timer Counter 2 UARTs (8250) for RS232 are incorporated in the PSC2 as a Mega The PSC2 incorporates 2 8-bit hardware free run counters necessary to Macro Function. UART1 and 2 are decoded as follows by the setting of control dedicated devices.
  • Page 74 3) When a card has been scanned, interrupts for the MCR interface (8) VFD Interface are activated. The PSC2 has 2 UARTs (8250) as Mega Macro Function. PSC+80XH 4) The main CPU reads taken card data from the FIFO buffer in the is used as the I/O address for this interface.
  • Page 75 17-5. PIN DESCRIPTION Signal name Function Signal name Function CTS2# RS-232 COM4/6 CTS DCD2# RS-232 COM4/6 DCD RI2# RS-232 COM4/6 RI Y737I SERAMIC RESONATOR CLOCK INPUT TXD1 RS-232 COM3/5 TXD Y737O SERAMIC RESONATOR CLOCK OUT- RXD1 RS-232 COM3/5 RXD DTR1# RS-232 COM3/5 DTR IS3# STD CKDC INTERRUPT REQUEST...
  • Page 76 Signal name Function Signal name Function MEMW# ISA MEMORY WRITE COMMAND from PIRQ3 INTERRUPT REQUEST 3 to CPU PIRQ4 INTERRUPT REQUEST 4 to CPU IOR# ISA I/O READ COMMAND from CPU PIRQ9 INTERRUPT REQUEST 8 to CPU IOW# ISA I/O WRITE COMMAND from CPU PIRQ10 INTERRUPT REQUEST 10 to CPU MCS16#...
  • Page 77 18. LAN CONTROLLER RealTak’s RTL8139C is used. 18-1. PIN ASSIGNMENTS 84 RTSET 83 LWAKE/CSTSCHG 82 RTT2 85 GND 86 RXIN- 81 RTT3 87 RXIN+ 80 GND 79 X1 88 OEB 89 WEB 78 X2 90 VDD 77 VDD 91 TXD- 76 PMEB 92 TXD+ 75 CLKRUNB...
  • Page 78 2) PCI INTERFACE Symbol Type Pin No Description AD31-0 120-123, 125-128, 4- PCI address and data multiplexed pins. 6, 8-11, 13, 26-29, 31- 34, 37-39, 41-45 C/BE3-0 2, 14, 24, 36 PCI bus command and byte enables multiplexed pins. Clock provides timing for all transactions on PCI and is input to PCI device. CLKRUNB Clock Run: This signal is used by RTL8139C(L) to request starting (or speeding up) the clock, CLK.
  • Page 79 Symbol Type Pin No Description MD0-7 108, 107, 105-100 Boot PROM data bus ROMCSB ROM Chip Select: This is the chip select signal of the Boot PROM. Output Enable: This enables the output buffer of the Boot PROM or Flash memory during a read operation.
  • Page 80 19. SYSTEM SWITCH 20. SYSTEM MEMORY Two 168pin DIMM Sockets are provided. 19-1. JUMPER SWITCH For Jumper Switch, switched signals are read by PSC2 in the hardware. 20-1. STANDARD MEMORY Giving a meaning to it is up to the software. 16777216 wordu64bit SDRAM Registered DIMM (Installed) Main PWB Single 3.3V(m0.3V) Power Supply...
  • Page 81 22-2. TOUCH PANEL CONTROL UART5 included in PSC2 as Mega Macro Function is used. The I/O address for this interface is PSC2 + (810h-817h) = 990h-997h. Command (CPU->Controller) Response Command Function Code Ope-code End Code Coordinate Code Notification Data RESET Controller initialization COLD-RST Coordinate initialization...
  • Page 82 This bit is designed for prevention of power OFF by manual The power switch of the UP-5900 is used to switch between terminal operation of Power Switch, and it has no effect on power ON state and stand-by state.
  • Page 83 Command Function Code US MD3 Horizontal Scroll Mode select 1Fh 03h ESC & s n m [a [p] sua] (m-n+1) Download text definition 1Bh 26h s n m [a [p] sua] (m-n+1) ESC ? n Download text delete 1Bh 3Fh ESC % n Download text set select/cancel 1Bh 25h...
  • Page 84 26. MAGNETIC CARD READER (MCR) 27-2. CONNECTOR SPECIFICATIONS (1) COM1 & COM2 26-1. OUTLINES D-SUB9 Targets are the UP-E12MR and the UP-E12MR2. Pin No. Signal Function 2ch MCR interface allows simultaneous read. Data Carrier Detect Each channel includes 96Byte FIFO. Receive Data Send Data 26-2.

  • Page 85: Chapter 6. Bios Setup Utility

    2-2. STARTING SETUP WITH FULL KEYBOARD Starting and operating setup with full keyboard will require UP-C30PK, In UP-5900, there is a utility that rewrites minimum required setup infor- PS/2 type full keyboard. mation at the system boot up that resides in ROM-BIOS.
  • Page 86 4. SETUP MENU Setup menu is as follows. Main Item Initial Value Description & Note System Time 00:00:00 Set System Time for battery backup RTC. Setting format is (HH:MM:SS). If RTC data is undefined, clock is initialized to 00:00:00 System Date 01/01/2002 Set System Date.

  • Page 87: Chapter 7. Hdi Recovery Procedures

    4. PRECAUTIONS This manual describes the procedures to recover the UP-5900 hard • Use of the UP-5900 Product Recovery CD-ROM is limited to the UP- disk image (HDI) to factory setup state. 5900. Never use it for other POS or PC.
  • Page 88 Create a boot FD for recovery according to “5. Creating bootable FDISK.EXE FD for recoverying HDI.” (3) Copy all files in [BOOT_FD] folder of the UP-5900 Product Recov- Connect the keyboard and USB-CD or SCSI+CD drive to UP-5900. ery CD-ROM into root folder (A:\) of “Windows98 startup disk” pre- Insert bootable FD for recovery into FD drive of UP-5900.
  • Page 89 2. Recovering FAT 3. Checking free clusters 4. Recovering the DOS partition There is no “suspend to disk partition” in UP-5900 HDI, so “5. Recovering the suspend to disk partition” will be skipped. (8) “Fdisk Options” are displayed. Select “1. Create DOS Partition or Logical DOS Drive” and press Enter key.
  • Page 90 (10) Enter the extended DOS partition size. For 15GB HDD, enter “7138” and press Enter key to return to the factory default size. (14) After completion of formatting, turn off power for the UP-5900 and connected devices, and remove USB-CD or SCSI card/CD-ROM drive.

  • Page 91: Chapter 8. About Utility Software

    CHAPTER 8. ABOUT UTILITY SOFTWARE The UP-5900’s utility softwere are provided by SHARP. 1. TOUCH PANEL CALIBRATION UTILITY PROGRAM [File name] : CALWINR. EXE [Out line] : This utility is for aligning press position and display position. This utility should be used to calibrate when following case is occurred.
  • Page 92 UP-5900VS CIRCUIT DIAGRAM 9 – 1...
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  • Page 97 UP-5900VS CIRCUIT DIAGRAM 9 – 6...
  • Page 98 MD43 MD42 MD41 MD40 MD39 MD38 MD37 MD36 MD35 MD34 MD33 MD32 MD31 MD30 MD29 MD28 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 MD19 MD18 MD17 MD16 MD15 MD14 MD13 MD12 MD11 MD10 UP-5900VS CIRCUIT DIAGRAM 9 – 7...
  • Page 99 UP-5900VS CIRCUIT DIAGRAM 9 – 8...
  • Page 100 SBA7 SBA6 SBA5 SBA4 SBA3 SBA2 SBA1 SBA0 UP-5900VS CIRCUIT DIAGRAM 9 – 9...
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  • Page 128 UP-5900VS PWB LAYOUT 10 – 1...
  • Page 129 UP-5900VS PWB LAYOUT 10 – 2...
  • Page 130 UP-5900VS PWB LAYOUT 10 – 3...
  • Page 131 UPPER SIDE BOTTOM SIDE UPPER SIDE BOTTOM SIDE UP-5900VS PWB LAYOUT 10 – 4...
  • Page 132  COPYRIGHT 2002 BY SHARP CORPORATION All rights reserved. Printed in Japan. No part of this publication may be reproduced, stored in a retrieval system, or transmitted. In any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without prior written permission of the publisher.