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Sharp UP-5700 Service Manual

Sharp UP-5700 Service Manual

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WIRING DIAGRAM
CHAPTER 1. SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
CHAPTER 2. OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
CHAPTER 3. SERVICE PRECAUTION. . . . . . . . . . . . . . . . . . . . . . 3-1
CHAPTER 4. DIAGNOSTICS SPECIFICATIONS . . . . . . . . . . . . . . 4-1
CHAPTER 5. CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 5-1
CHAPTER 6. POWER SUPPLY UNIT . . . . . . . . . . . . . . . . . . . . . . . 6-1
CHAPTER 7. BIOS SET UP UTILITY . . . . . . . . . . . . . . . . . . . . . . . 7-1
CHAPTER 9. CIRCUIT DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
CHAPTER 10. PWB LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Parts marked with "
" is important for maintaining the safety of the set. Be sure to replace these parts with specified
ones for maintaining the safety and performance of the set.
SERVICE MANUAL
CONTENTS
SHARP CORPORATION
POS TERMINAL
UP-5700
MODEL
("U" & "A" version)
This document has been published to be used
for after sales service only.
The contents are subject to change without notice.

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  • Page 1: Table Of Contents

    SERVICE MANUAL POS TERMINAL UP-5700 MODEL ("U" & "A" version) CONTENTS WIRING DIAGRAM CHAPTER 1. SPECIFICATIONS ......1-1 CHAPTER 2.
  • Page 2 SHARP product service centers. You may also contact your local recycling center for information on where to return the spent battery pack. SHARP’s involvement in this program is part of its commitment to protecting our environment and conserving natural resources.

  • Page 3: Chapter 1. Specifications

    3-3. PC system CHAPTER 1. SPECIFICATIONS ITEM SPECIFICATIONS NOTE Pentium processor 1. Appearance Chip set OPTI 82C700 VGA chip C&T T65550B Main memory Standard: 8 Mbytes EDO type Flat-panel LCD display (for executing MS-DOS, with touch-sensitive overlay Max.: 40 Mbytes adding S.O.DIMM Application software) Video RAM...
  • Page 4 You must not use this shutdown switch when the UP-5700 is running normally. Use this switch only when the main power source is not cut off even if the main unit power switch is set to OFF position. UP-5700 The PSC2 simply reads switched signals from the DIP switch as is turned OFF and the hardware is reset by turning the main power hardware.
  • Page 5 BIOS Hardware Power switch Provided from SHARP The power switch is used to turn the POS terminal on or stand-by If the communication function is used, the AC power can be turned off by software operation for power saving after communication.
  • Page 6 Touch panel calibration utility program (MS-DOS) — ... These software are provided with FD from SHARP. Please copy contents of FD provided from department to development PC. Install to UP-5700 by using APL Install Program from PC. 4-3. Memory map 0000000h...

  • Page 7: Chapter 2. Options

    CHAPTER 2. OPTIONS 1. System configuration Incorporated in Main Unit RS-232 Communication Connection Master Machine UP-5700 AT Keyboard <supplied on site> (RS-232) max.6 max.2 RS232 Board Remote Printer <Option> <Option> ER-01PU Drawer Additional ER-A8RS <supplied on site> TM-T80/85/295 <Option> RAM Memory...

  • Page 8: Chapter 4. Up

    PARTS CODE PRICE DESCRIPTION Service tool kit ISA checker ISA relay board RAM relay board (Not used for UP-5700) Printer connector signal loop back connector for ER-A8RS CENTRONICS connector MCR test card for UP-E12MR RS232 loop back connector for RS232 connector...
  • Page 9 Connected to the ISA checker for installation of the optional I/F hori- zontally and for repairing and checking the operation . External view ISA checker 3) RAM PWB relay board (UP-5700: Not used) External view Plan view ISA bus connector:...
  • Page 10 Plan view and connection diagram 4-4. RS232 loop back connector: UKOG-6705RCZZ Connected to the RS232 connector (D-SUB 9 pin: COM1, COM2, COM3, COM4) of the UP-5700 and ER-A8RS, and used to check loop signals when executing diagnostics. 150±8 Connection diagram 1pin Signal name Pin No.
  • Page 11 The CPU PWB, you can check the soldered face of the CPU PWB by The BIOS loading board: CKOG-6727BHZZ is a tool to write a BIOS connecting the CPU PWB to the VGA PWB. ROM program in the F-ROM on the UP-5700’s main board. Use this PWB in the following cases: External view The F-ROM on the UP-5700’s main board is changed due to some...
  • Page 12 Plan view Writing BIOS ROM Program 1. Install the EP-ROM (master ROM): VHI27040RBH1A containing a BIOS program on the BIOS loading board: CKOG-6727RCZZ. BIOS MASTER ROM LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 Connection diagram 2 – 6...
  • Page 13 2. Set SW1 on the BIOS loading board to the side of pin 3. 4. Connect the BIOS loading board to the option ROM/RAM connec- tor CN19 on the main PWB, and then close the cabinet. LED9 5. Writing the BIOS ROM program starts by turning on the power switch on the right side.
  • Page 14 LED DISPLAY STATUS [ : ON (Lighting) — : OFF] <In normal operation> LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 LED9 FUNCTION (RED) (RED) (RED) (RED) (RED) (RED) (RED) (RED) (GREEN) — Start of COPY FUNCTION — — — —...

  • Page 15: Chapter 3. Service Precaution

    CHAPTER 3. SERVICE PRECAUTION 1. Conditions for soldering circuit parts To solder the following parts manually, follow the conditions described below. PARTS NAME PARTS CODE LOCATION CONDITIONS FOR SOLDERING Ceramic oscillator MAIN PWB: X1 (8M) 270°/3sec. MAIN PWB: X2 (24M) MAIN PWB: X2 (7.37M) DIP SWITCH MAIN PWB: S3...
  • Page 16 (1). The UP-5700 can be externally connected to a keyboard. Replacement parts required when the OCNCW7218RC3J’s The UP-5700’s key BIOS conforms to the PC standard, but this slider is broken BIOS’s operation is not assured for some keyboards.
  • Page 17 1) Rear Display Check ......10 2) Connect the AT keyboard. 3-12. SHARP Retail Network Diagnostics ....11 3) Turn the main power ON to start up the BIOS-ROM (MASK 1) SRN Self Check .

  • Page 18: General

    When the selected diagnostics program is completed, the display 2. System configuration returns to the menu screen. Pressing Esc key returns to the service diagnostics menu. The system requires the UP-5700 body, HDD or FDD, and the AT keyboard for diagnostic operations. RAM Diagnostics D-RAM Check Standard RAM Disk Check 3.

  • Page 19: Standard Ram Disk Check

    2) Standard RAM Disk Check v. Test data 5555H is written to the test area. Check content vi. Test data and read data are compared. If is OK, test data AAAAH is written to the test area. For the standard RAM disk area (BANK 000H 03FH), each test area of bank size 16KB is checked.

  • Page 20: Bios Rom Check

    2) BIOS ROM Check Terminating method Check content After the test result is displayed, press Esc key to terminate, The BIOS ROM version is displayed. 4) Option FLASH ROM Check Display Check content Write read verify check or read check is performed for the option BIOS ROM Check FLASH ROM area (BANK 280H –...

  • Page 21: Real Time Clock & Cmos Ram Diagnostics

    The error address and the error bit are displayed only when an 3-5. Real time clock & CMOS RAM Diagnostics error occurs. (When no error occurs, they are not displayed.) RTC and CMOS RAM check is performed. Terminating method The following menu is displayed. The highlighted cursor is moved by After the test result is displayed, press Esc key to terminate.

  • Page 22: Touch Key Pad Test

    2) Touch Key Pad Test 3-7. Clerk Key Diagnostics Check content The clerk key input test is performed. The driver function call is used. Pressing Esc key returns to the serviceman diagnostics menu. is displayed at the four corners of the LCD sequentially. 1) Clerk Key Check (In the sequence of upper right, upper left, lower left, lower right.) Check content...

  • Page 23: Parallel2 Loop Check

    Fig, 3-4 is connected with PARALLEL2 (ER-A8RS) and PARAL- LEL1 for testing. Set the jumper on the PWB during the test as shown in Fig. 3-6. ACK- ACK- UP-5700 : PARALLEL1 INPUT MODE BUSY BUSY A8RS : PARALEL2 OUTPUT MODE SLCT...

  • Page 24: Parallel3 Loop Check

    PARALLEL1 for testing. Set the jumper on the PWB during the test as shown in Fig. 3-6. "PARALLEL1 Channel Disabled" is displayed only when no ac- cess to PARALLEL1 is allowed. UP-5700 : PARALLEL1 OUTPUT MODE Terminating method. A8RS : PARALEL3 INPUT MODE Press Esc key to terminate.

  • Page 25: Parallel3 Print Check

    Therefore, when an ER-A8RS is used, you must set COM1, 2, 5, and 6 on the UP-5700 side, and set COM3 and 4 on the ER-A8RS side. The following menu is displayed. The highlighted cursor is moved by the cursor keys (UP and DOWN ) of the AT keyboard.

  • Page 26: Com2 Check

    When the ER-A8RS is assigned to COM3, the check procedure, display and terminating method are the same as COM1. When the RJ-45 port of the UP-5700 main unit is assigned to COM3, the following points are different from COM1 Check : Content RTS-CTS is not checked.

  • Page 27: Rear Display Diagnostics

    vi. Reversed pattern of pattern v. Arrange RAMDAC register No. 0 255 from the upper left. vii. "H" pattern (80 digits 35 lines) In the 35th line, only 78 digits of "H" are displayed. (The actual display range is 25 lines. Scroll for 10 lines to check.) xii.

  • Page 28: Sharp Retail Network Diagnostics

    Diag 0 command is executed and the error status is dis- 3-12. SHARP Retail Network Diagnostics played. The error status is as shown in the table below. When The SRN interface option ER-01N-PC is tested. an error occurs in this test, the following test is not executed.

  • Page 29: Srn Flag Send Check

    The error status from the controller to the host is as shown in 4) Data Transmission Check the table below. Data transmission test is executed in an actually constructed system. The system is composed of one master machine and max. 15 satel- NC (Always displays "0.") lite machines.

  • Page 30: Magnetic Card Reader Diagnostics

    The error codes are as shown in the table below. Data Transmission Check (Master Machine) Command abnormality (except for during transmission) XXX shows the read Master Terminal No. : xxx Terminal No. No received data Input Satellite Terminal No. : 0000 XXX shows the entered Terminal No.

  • Page 31: System Switch Diagnostics

    Display Drawer Diagnostics MCR (Magnetic Card Reader) Check Drawer 1 Check TRACK1: Drawer 2 Check SHARP TEST CARD 0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789 UKOG-6718RCZZ TRACK2: 0123456789012345678901234567 1) Drawer 1 check The above display is made when UKOG6718RCZZ is passed Check content through the MCR. In case of an error, the error code is displayed...

  • Page 32: Ide I/F & Hard Disk Diagnostics

    ii. The test pattern with all digits ON is displayed. Display Drive Status display hard disk drive information Drive Type : xxxxxx Capacity : xxxxMB Cylinder Number : xxx Head number : xx Sector number : xx iii. All OFF Press any key to exit.

  • Page 33: Random Seek Test

    On the above screen, when pass count is counted up (when point (Head movement) is counted up to the upper limit set in the cylinder range setting, When track N is read, the head moves as follows: the pass count is counted up by 1.), and if the error counter of all error items are not counted up (remaining as 00000), the test is The previous The next...

  • Page 34: Hd Dump Test

    Error stop/Continue/1 Pass Check content Selection is made among Error Stop/Continue/1 Pass in case The sector set in the above is displayed on the screen in the unit of an error. of 256byte. Test start ? [Yes/No] Hex data and ASCII characters are displayed. Selection is made between Yes/No of test start.

  • Page 35: Contoroller Check Test

    Error Content YY/MM/DD HH : MM : SS The correct password is "sharp" or "SHARP" in 5 digits. When XXXXXXX 92 / 03 / 01 10 : 30 : 00 typing the correct password, the content is not displayed but " " is displayed.

  • Page 36: Target Sector Write/Read-Verify Test

    (Worst pattern data) Hex data and ASCII characters are displayed. There are two kinds of worst data: B6DBH and 6DB6. By key operation, the following 256 byte data or previous 256byte data can be displayed. In case of an error during the above test, retry is repeated up to the set number of retry.

  • Page 37: Error Content

    15) Error content 3-18. Fan & LCD ON/OFF Diagnostics The following error content is error information directly obtained from 1) Fan & LCD ON/OFF Check the HDD controller. Check content [Error code and meaning] The CPU, the fan, the exhaust fan and the LCD are turned Error code Error message ON/OFF.

  • Page 38: Chapter 5. Circuit Description

    Clerk Switch Sense: 16bits (UP-5700 supports 76 its clerks) CHAPTER 5. CIRCUIT DESCRIPTION MCR I/F: 2track Drawer I/F: 4drawers (UP-700 supports 2drawers.) 1-7. Memory L2 cache: None 1-1. CPU System Memory: DRAM Standard = 1M 16b EDO Pentium Processor: A80502CSLM66133SY028 Asym 60ns Vcc = 3.3V...

  • Page 39: Block Diagram

    COM3/5 (for serial device): RJ45 (+ 5V possibility with Pattern-cut 1-14. Options & Jumper) [New] COM4/6 (for serial device): RJ45 UP-P02MB: Expansion RAM Disk Board (2MB [ COM7 16Bus]) (for Operator VFD control): Not use UP-F4RB: Expansion ROM Disk Board (4MB [ COM8 16Bus]) (for Customer VFD control): RJ45...

  • Page 40: Memory Map

    3. Memory Map Main Memory BIOS Memory (System) (ROMCS/MROMCS/FROMCS/RAMCS) 0000000 EDO DRAM Standard A0000 VGA RAM 0800000 128KB EDO DRAM Option 8Byte SOD 1000000 EDO DRAM Option 8Byte SOD 16MB 1800000 EDO DRAM C0000 Option 8Byte SOD VGA BIOS 32MB 40KB C9FFF CC000...
  • Page 41 4. I/O Address Map Address Legacy ISA I/O 800-A78 Address Legacy ISA I/O (PnP ISA Auto Configuration Port) 00-0F DMA ch0-3 control A7A-CF7 10-1F (System) CF8-CFF PCI Configuration 20-21 Master 8259 Interrupt control D00-FFF 22-24 Chipset Configuration 40-43 Timer control Address POS I/O 48-4B...
  • Page 42 6. IRQ 6-1. IRQ Mapping list Master Slave PSC2 ISA Slot Penrium UP-5700 8259 8259 IRQ0 Timer FireStar PIRQ9 IRQ9 IRQ9 IRQ9 IRQ1 2.7K IRQ2 (Cascade) IRQ15 PIRQ15 IRQ15 IRQ15 IRQ8 RTC/CMOS 2.7K Mask n IRQ9 IRQX IRQn IRQ10 COM4/ISA...
  • Page 43 Frequency (max) Ratio (Y33) (Y35) 150MHz 60MHz 133MHz 66MHz 120MHz 60MHz UP-5700 Setting 100MHz 66MHz 90MHz 60MHz 75MHz 50MHz Setting 1 = 10kohm Pull up (Vcc3) 0 = 0ohm Grounding Micro Clock MK1438-04R Clock Generator CPU Clock Decording Table ( TENTATIVE)
  • Page 44 7-2. Pin assignments FLUSH# VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC3 VCC3 VCC3 VCC3 VCC3 EADS# HTM# BUSCHK# BE0# BE2# BE4# BE8# SCYC HIT# A20M# BE1# BE3# BE5# BE7# RESET BREQ HLDA ADS# LOCK# SMACT# VCC3 VCC2 PCHK# VCC2 APCHK# VCC3 VCC2 PRDY...
  • Page 45 7-3. Pin description Table 4. Quick Pin Reference Symbol Type Name and Function A20M# When the address bit 20 mask pin is asserted, the Pentium processor emulates the address wraparound at 1 Mbyte which occurs on the 8086. When A20M# is asserted, the processor masks physical address bit 20 (A20) before performing a lookup to the internal caches or driving a memory cycle on the bus.
  • Page 46 Symbol Type Name and Function EWBE# The external write buffer empty input, when inactive (high), indicates that a write cycle is pending in the extemal system. When the processor generates a write and EWBE# is sampled inactive, the processor will hold off all subsequent writes to all E-or M-state lines in the data cache until all write cycles have completed, as indicated by EWBE# being active.
  • Page 47 Symbol Type Name and Function PCHK# The parity check output indicates the result of a parity check on a data read. It is driven with parity status two clocks after BRDY# is returned. PCHK# remains low one clock for each clock in which a parity error was detected. Parity is checked only for the bytes on which valid data is returned.
  • Page 48 8. Chipset 8-1. Introduction OPTi’s FireStar ACPI (82C700U2.2) is used. FireSter Strap Options Pin No. Pin Name Internally at Reset Setting Function RTCRD# Pull low Pull high (Vcc5) PCICLK1 Enable RTCWR# Pull low Default PCICLK2 Disable ROMCS# Pull low Default PCICLK3-5 Disable KBDCS# Pull low...
  • Page 49 8-2. Pin assignments HD48 HD49 HD50 HD52 HD55 HD59 SDCKE* TAG4 TAG- CAS3# CAS7# MD61 MD56 MD52 MD47 MD42 MD38 MD33 MD29 MD25 MD22 MD20 CAS# H46D HD47 HD51 HD53 HD56 HD60 RSVD TAG7 TAG3 CAS0# CAS4# RAS2# MA10 MD60 MD55 MD51 MD46...
  • Page 50 8-3. Pin description 8-3-1. CPU Interface Signals Set Signal Type Signal Name Pin No. Selected By Signal Description (Drive) Host Data Bus HD[63:0] Refer to Host Data Bus Lines 63 through 0: Provides a 64-bit data path to Table 3-2 (4mA) the CPU.
  • Page 51 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) Next Address: This signal is connected to the CPU’s NA# pin to (4mA) request pipelined addressing for local memory cycle. FireStar asserts NA# for one clock when the system is ready to accept a new address from the CPU, even if all data transfers for the current cycle have not completed.
  • Page 52 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) GWE# SYSCFG Global Write Enable: Write command to L2 cache indicating that all (4mA) 19h[7] = 0 bytes will be written. RAS5# SYSCFG Row Address Strobe Bit 5: Each RAS# signal corresponds to a 19h[7] = 1 unique DRAM bank.
  • Page 53 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) TAG7 SYSCFG Tag RAM Data Bit 7: This input signal becomes an output whenever (4mA) 11h[3] = 0 TAGWE# is activated to write a new tag to the Tag RAM. CAS7# SYSCFG Column Address Strobe Bit 7 (2nd copy)
  • Page 54 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) RAS3# Cycle Row Address Strobe 3: Refer to RAS0# signal description. (8/12mA) Multiplexed SDCS3# SDRAM Chip Select Line 3: Refer to SDCS0# description. MA12 PCIDV1 Memory Address Bus Line 12 53h[6:3] = 01 RAS4# SYSCFG...
  • Page 55 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) IRDY# AB11 Initiator Ready: IRDY# indicates FireStar’s ability, as an initiator, to (PCI) complete the current data phase of the transaction. It is used in conjunction with TRDY#. A data phase is completed on each clock that both IRDY# and TRDY# are sampled asserted.
  • Page 56 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) GNT1# AB17 Default PCI Bus Grant 1: GNT# is returned to PCI bus masters asserting (PCI) REQ#, when the bus becomes available. PCICLK1 RTCRD# strap PCI Clock Output 1 (4mA) option REQ2#...
  • Page 57 8-3-4. ISA Interface Signal Set Signal Type Signal Name Pin No. Selected By Signal Description (Drive) Interrupt Controller Interface IRQ1 AF18 PCIDV1 Interrupt Request 1: Normally connected to the keyboard controller. 8Ah = 00h IRQ1 is a 5.0V tolerant input, even when its power plane is connected to 3.3.V as long as the 5VREF pins of FireStar are connected to +5.0V.
  • Page 58 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) IRQSER AE18 PCIDV1 Serial interrupt Request: Bidirectional interrupt line for Compaq BAh[0] = 0 style of serial IRQs. SDCKE PCIDV1 SDRAM Clock Enable: This signal is asserted to put the SDRAM 53h[4] = 1 into a "Stop"...
  • Page 59 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) DACKC#/DACK2# Programmable DMA Acknowledge C/DACK2#: DACK# is used to acknowledge DRQ to allow DMA transfer. This input defaults to DACK2#, however, it can be programmed to route onto any internal DACK# by programming PCIDV1 C1h[2:0]. PPWR6 PCIDV1 Peripheral power control Line 6...
  • Page 60 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) ATCLK AA22 ISA Bus Clock: This signal is derived from an internal division of (8mA) PCICLK. It is used to sample and drive all ISA synchronous signals. PCIDV1 47h[5:4] sets the ATCLK: 00 = PCICLK+4 10 = PCICLK+2 01 = PCICLK+3...
  • Page 61 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) PCIDV1 Address Enable: AEN is asserted during DMA cycles to prevent I/O C2h [1] = 0 slaves from misinterpreting DMA cycles as valid I/O cycles. When asserted, AEN indicates to an I/O resource on the ISA bus that a DMA transfer is occurring.
  • Page 62 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) Note: XD[7:0] can be strapped to be dedicated IDE lines via the RTCAS:A20M# strap option and PCIDV1 75h[6] = 1 SA[23:20] V23:V26 System Address Bus Lines 23 through 20: The SA[23:0] signals (8mA) on FireStar provide the address for memory and I/O accesses on the ISA bus.
  • Page 63 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) SPKROUT Speaker Data: This pin is used to drive the system board speaker. (8mA) This signal is a function of the Timer-0 Counter-2 and Port 061h bit 1. Can use CISA Protocol to gang several. KBDCS# Default PCIDV1 Keyboard Chip Select: Used to decode accesses to the keyboard...
  • Page 64 9-1. Introduction The keyboard and mouse are controlled using Mitsubishi Electric’s M38802M267. No mouse can be used for UP-5700 because IRQ12 is not con- nected. In addition, A20M# of M38802M2 is not used because Fire- star’s A20M# is used. M38802M2 Port5 Jumper Options Pin No.
  • Page 65 Name Features Features other than port P50/R D, I/O port P5 4-bit I/O port with almost the same feature as P0. Serial I/O pin P51/T D, CMOS input level is used, and the form of output P52/SCLK, is CMOS 3-state. P53/S R D Y P60/INT5/ I/O port P6...

  • Page 66: Video Subsystem

    Upper 4 bits of each 6 bits are connected to 12 bits (4 bits for red, green, and blue respectively) of LCD . UP-5700 connects a PCI bus as interface, and uses 2 chips of EDO DRAM configured in 256K 16 as graphic memory so that the total capacity is 1M bytes.
  • Page 67 10-2. Pin assignments DRAM "A" DRAM "B" Video Port & Display Memory Display Memory DRAM "C" Lower 512KB Upper 512KB (WEAH#) WEA# (WEAB1#) (WECL#) (VP14/VR6) CASCL# MVCCA (CASC#) (VP15/VR7) CASCH# (CASA#) CASAH# Configurmion Pins (WECH#) (PCLK) WEC# (WEAL#) CASAL# LB# = 0 PCI Bus (Default) (KEY) (VRDY) RASC#...
  • Page 68 10-3. Pin description 10-3-1. CPU Direct/VL-Bus Interface Pin names in parentheses (...) indicate alternate functions. Pin# Pin Name Type Active Description RESET Reset. For VL-Bus interfaces, connect to RESET#. For direct CPU local bus interfaces, connect to the system reset generated by the motherboard system logic for all peripherals (not the RESET# pin of the processor).
  • Page 69 Pin# Pin Name Type Active Description High System Data Bus. In 32-bit CPU Local Bus designs these data lines connect directly to the processor High data lines. On the VL-Bus they connect to the corresponding buffered or High unbuffered data signal. High These pins are tri-stated during Standby mode (as are all other bus interface High...
  • Page 70 10-3-2. PCI Bus Interface Pin# Pin Name Type Active Description RESET# Reset. This input sets all signals and registers in the chip to a known state. All outputs from the chip are tri-stated or driven to an inactive state. This pin is ignored during Standby mode (STANDBY# pin low).
  • Page 71 Pin# Pin Name Type Active Description ROMA0 HIgh BIOS ROM address outputs. See MAD8-15 (pins 170-177) for BIOS ROM data inputs. ROMA1 (GPIO3) High ROMA2 (GPIO4) High BIOS ROMs are not normally required in portable computer designs ROMA3 (GPIO5) High (Graphics System BIOS code is normally included in the System BIOS ROMA4 (GPIO6) High...
  • Page 72 Pin# Pin Name Type Active Description C/BE0# Bus Command / Byte Enables. During the address phase of a bus transaction, these pins define the bus command (see list above). During the C/BE1# data phase, these pins are byte enables that determine which byte lanes C/BE2# carry meaningful data: C/BE3#...
  • Page 73 10-3-3. Display Memory Interface Pin# Pin Name Type Active Description MAD0 (TSENA#) High Memory data bus for DRAM A (lower 512KB of display memory) MAD2-7 are latched into XR71 on reset for use as additional configuration inputs MAD1 (ICTENA#) High (CFG10-12 are reserved by software for input of panel ID).
  • Page 74 10-3-4. Flat Panel Display Interface Pin# Pin Name Type Active Description High 8, 9, 12, or 16-bit flat panel data output. 18-bit and 24-bit panel interfaces may also be supported (see CA0-7 for P16-23). High Refer to the table on the next page for the configurations for various panel types. High High High...
  • Page 75 10-3-5. CRT & Clock Interface Pin# Pin Name Type Active Description HYSNC (CSYNC) Both CRT Horizontal sync (polarity is programmable) or "Composite Sync" for support of various external NTSC / PAL encoder chips. Note CSYNC can be set to output on the ACTI or ENABKL pins.
  • Page 76 10-4. Functional block diagram 11. Super I/O The 65550 system configurations appear below. Figure 1 shows the connections to external hardware: 11-1. Introduction The FDC, serial port COM1 and COM2, and parallel port LPT1 are controlled by ALi’s M5113A2. Option I M5113 Hardware Setting Configuration NTSC/PAL Video Input...
  • Page 77 11-3. Pin description A low represents a logic 0 (0V nominal) and a high represents a logic 1 (+2.4V nominal). Name Number Type Description HOST Processor Interface D0-D7 48-51, 53-56 I/O24 Data bus. This connection is used by the host microprocessor to transmit data to and from the M5113. These pins are in a high impedance state when not in the output mode.
  • Page 78 Name Number Type Description WRTPRTJ Write Protected. This active-low Schmitt Trigger input senses from the disk drive that a disk is write- protected. Any write command is ignored. TRK0J Track 00. This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the outermost track.
  • Page 79 Name Number Type Description DRV2 Drive 2. In PS/2 mode, this input indicates whether a second drive is connected: this signal should be low if a second drive is connected. This status is reflected in a read of Status Register A. ADRxJ Optional I/O port address decode output.
  • Page 80 Type Descriptions: Input TTL compatible Input with Schmitt Trigger I/O20 Input/Output with 16 mA sink 0.4 V, source 16 mA 2.4 V I/O24 Input/Output with 24 mA sink 0.4 V, source 12mA 2.4 V I/O36 Input/Output with 36 mA sink 0.4 V, source 8 mA 2.4 V ICLK...
  • Page 81 Bank base address + 004000H to 007FFFH Bank 080H to 0BFH 12-1. PSC2 Feature Outline PRAS3 area: Sharp’s LZ9A10000 is used as the PSC2, controlling the POS device Bank base address + 004000H to 007FFFH Bank 000H to 1FFH connected to the ISA bus.
  • Page 82 The PSC2 internal interrupt expansion consists of a maskable inter- SCKF is outputted to SCK pin without the logic changed and preset to rupt source register (ISR), which is the source of interface OR-com- "1" by RESET. The serial data is in the form of LSB first. SCKF posed from each interrupt input, interrupt mask register (IMR) control- operates with synchronized with SCK, and the operation speed de- ling the mask control , status read level register (SRL) reading the...
  • Page 83 2) After a card is scanned, the MCR interface changes serial data of 12-3-8. VFD Interface the MCR to parallel data. Changed data is written in the FIFO The PSC2 has 2 UARTs (8250) as Mega Macro Function. buffer at every character in order from the start mark to the LRC. PSC+80XH is used as the I/O address for this interface.
  • Page 84 12-5. Pin description Signal name Function Signal name Function CTS2# RS-232 COM4/6 CTS Y737I SERAMIC RESONATOR CLOCK DCD2# RS-232 COM4/6 DCD INPUT RI2# RS-232 COM4/6 RI Y737O SERAMIC RESONATOR CLOCK TXD1 RS-232 COM3/5 TXD OUTPUT RXD1 RS-232 COM3/5 RXD DTR1# RS-232 COM3/5 DTR IS3# STD CKDC INTERRUPT REQUEST...
  • Page 85 Signal name Function Signal name Function MEMW# ISA MEMORY WRITE COMMAND SA23 ISA BUS SA23 from CPU IOR# ISA I/O READ COMMAND from CPU PIRQ3 INTERRUPT REQUEST 3 to CPU IOW# ISA I/O WRITE COMMAND from CPU PIRQ4 INTERRUPT REQUEST 4 to CPU MCS16# MEMORY CHIP SELECT 16 to CPU PIRQ9...
  • Page 86 DWS-4 Drive C:, D: & E: Setting Drive C: Drive D: Drive E: SW-4 SW-5 15-1. Outline — — Sharp’s LH28F004SUT-NC80 (value = 0) (value = 0) Flash Composed of erase blocks divided into 16KB even blocks PS RAM (value = 0)
  • Page 87 19. Analog Touch Panel 17-1. Outline 19-1. Outline Sharp’s LH28F016SUT-10 The analog touch panel is controlled by Fujitsu’s control IC N010- 0559-V021, and the CPU issues commands to this panel through Composed of erase blocks divided into 64KB even blocks serial interface.
  • Page 88 20-2. Timing Chart 20-4. Shutdown Control The power switch of UP-5700 is used to switch the ON state and stand-by state of terminal. PWGOOD When starting up the terminal, the power switch is necessary to be set ON. When the power switch is set to the position of stand-by (200ms) mode, the power source unit stops automatically.
  • Page 89 4) The main CPU reads card data from the FIFO buffer in the inter- 22. Drawer rupt handling. The main CPU can read the data using IN com- mand of 0WAIT. 22-1. Outline Even after the LCR which is the last character of a card was read, ER-03DW, ER-04DW, and ER-05DW support 2 channels but only 10 to 20 characters of "0"...
  • Page 90 24-2. Connector Specifications (1) COM1 & COM2 D-SUB9 Pin No. Signal Function Data Carrier Detect Receive Data Send Data Data Terminal Ready Signal Ground — Data set Raedy Request to Send Clear to Send CI/+5V Ring Indicate/+5V I/— (2) COM3/5 RJ45 Pin No.

  • Page 91: Chapter 6. Power Supply Unit

    CHAPTER 6. POWER SUPPLY UNIT 1. General This power unit is used for UP-5700. The AC input voltage is AC90 138V. The safety standard conforms to Electrical regulations UL1950.CSA950.SS-J. The outputs are +5V, +12V, and –12V. The other functions include ACL signal, PHSNS signal, PHOLD signal, overvoltage protection against power abnormality, and overcurrent protection which protects the power from an overload.
  • Page 92 3. Operational description As shown in the block diagram, the commercially available AC voltage supplied through the AC cord passes through the N/F section to the rectifying section where it is smoothed to about 140V then supplied to the invertor section. The switching system of the invertor section is with one-stone ON/OFF self excitement invertor (RCC system).
  • Page 93 3-3. +12V, –12V output section 1SS270A +12V FMB26L +12V 330µF SI-3122N 100µF 104K PW(PY) (PY)(LXJ) 13,14 FMB29L 330µF 100µF 104K PW(PY) PW(PY) (LXJ) -12V UPC337H (HF) 1SS270A The +12V/–12V output section supplies a stable voltage with the regulator IC (IC3, IC4). The overcurrent protection function is built in the regulator 3-4.

  • Page 94: Troubleshooting

    3-7. Overcurrent protection function When the output current on the primary side becomes overload, the drain current is detected by R11 to turn on Q2 and control Q1 gate voltage to shorten ON period of Q1, protecting against overload. 3-8. Overvoltage protection function The overvoltage protection circuit is composed of R21, D11, D14, and PC3.
  • Page 95 4-2. +12V is not supplied. START Are +5V and -12V 1. In case of all outputs stop, refer to the +5V troubleshooting. Repair supplied normally ? Is the voltage 1. When the voltage between IC3 1-3 pin is 12.5V or lower, +12V at IC3 1-3 pin 12.5V Repair or more ?
  • Page 96 4-4. ALC is not supplied. START 1. If +5V is not supplied, the ALC is not supplied. Are +5V and +12V Repair 2. If +12V is not supplied, the ALC detecting IC5 does not oper- supplied normally ? ate. 1. R30, 31, 32 trouble may be the cause. Is the voltage across C26 13V Repair...
  • Page 97 Fig-2 Q1: Rated load Fig-3 Q1: No load 10µs/DIV 10µs/DIV 1SS270A +12V FMB26L P1165 5D-11 +12V 0.01µF 100K D3SB60 104K 630V 330µF SI-3122N 100µF (RBV-406) 820µF 200K 200V PW(PY) (PY)(LXJ) 2200µF/10V PW(PY) 100µF/10V SBC6-4R7-802 GU(NSN) AG01 x 2 PW(PY) 11,12 C30 C31 C32 C33 2200PF ENC112D-10A...
  • Page 98 Fig-5 T1 : Between 11,12-13,14pin Fig-6 T1 : Between 8-9pin 10µs/DIV 10µs/DIV 1SS270A +12V FMB26L 5D-11 P1165 +12V 0.01µF 100K D3SB60 104K 630V 330µF SI-3122N (RBV-406) 100µF 820µF 200K 200V PW(PY) 2200µF/10V PW(PY) 100µF/10V (PY)(LXJ) GU(NSN) SBC6-4R7-802 AG01 x 2 PW(PY) 11,12 C30 C31 C32 C33...
  • Page 99 6. Input/output specifications 6-1. Input specifications Input voltage: AC90V AC138V Input frequency: 48Hz 62Hz Number of input phases: Single phase 2-line system Rush current: 40A or less, AC138V, rated load (When in cold start, at 25°C) 6-2. Output specifications Item +12V –12V Load current range...

  • Page 100: Chapter 7. Bios Setup Utility

    Procedure for starting setup is as follows. 1. Outline Start the system. In Up-5700, there is an utility that rewrites minimum required setup Press following keys according to setup wanted while SETUP information at the system bootup which resides in ROM-BIOS.
  • Page 101 ................Phoenix NoteBIOS 4.0.x RAM token Copyright 1985-1997 Phoenix Technologies Ltd., All Rights Reserved Message displayed by parity error from bus (position undefined) SHARP POS Terminal Firmware Version 1.0A Message Error meaning CPU = Pentium xxxMHz ..............0000640K System RAM Passed...

  • Page 102: Chapter 8. About Utility Software And Others

    To adjust it, use the touch pen of K-PDA (Keyboard enhanced Per- sonal Digital Assistant). Two types of UP-5700’s utility software are provided by Sharp: one is used on UP-5700, and the other one is used on a PC (personal PARTS CODE PARTS NAME MODEL computer).

  • Page 103: Chapter9. Circuit Diagram

    CHAPTER9. CIRCUIT DIAGRAM MAIN PWB VGAC T655550 1/16 VCC3 MAD5 MAD4 MAD3 VCC3 AA[0..8] "L" "H" "L" A88X MONO BR20 "L" "H" "H" A85X MONO STNDBY# "H" "L" "L" A8CX 18bit MBD[0..15] "H" "L" "H" A88X 12bit BR21 22Kx4 MAD[0..15] 4.7Kx4 C/BE#[0..3] C/BE#[0..3]...
  • Page 104 VGA-RTC,2.9V PS 2/16 VCC5 VRAM VCC5 IC21 C195 R238 VCC5 RCL# R251 RCL# C200 C199 C196 1000p 0.1u 0.1u RTCAS 32.768kHz RTCAS RTCRD# RTCRD# RTCWR# RTCWR# R/W# IRQ8 IRQ8 INT# RSTDRV# RST# EXTRAM BQ3285ESS 24pin SSOP IC23D 74HC08 VCC5 IC22D IC27 1/2W 0.033 F 0.1u...
  • Page 105 VGA CONNECTOR 3/16 C/BE#[0..3] C/BE#[0..3] VCC2 VCC2 CN14 VCC3 AD[0..31] AD[0..31] BR19 BR16 C/BE#0 10KX4 10KX4 C/BE#1 C/BE#2 C/BE#3 FRAME# FRAME# IRDY# IRDY# TRDY# TRDY# DEVSEL# DEVSEL# STOP# STOP# CPAR CPAR SERR# SERR# AD10 PERR# PERR# AD11 AD12 DBEW# AD13 DDRQ AD14 DCS3#...
  • Page 106 PSC2 4/16 VCC5 VCC5 BR12 10Kx4 CLS1 R204 R203 RDD1 BR13 RCP1 10Kx4 CLS2 RDD2 RCP2 SIOCS# RXD9 TXD9 VCC5 DSR8# DTR8# TXD8 MODR VCC5 CFSR CTS4# 7.37M VCC5 Y737I RTS2# RTS4# Y737O DSR2# DSR4# R206 R205 BALE BALE DTR2# DTR4# RXD2 RXD4...
  • Page 107 RTC,MKey,IDE 5/16 47pX12 VCC5 C144 C142 C140 C131 C129 C127 C132 C130 C145 C143 C141 C128 KEY Controller CN15 VCC5 RSTDRV# RSTDRV# TXD9 TXD9 VCC5 RDX9 KSTB[0..11] RXD9 KSTB0 KSTB1 KSTB2 +12V KSTB3 CFSR CFSR KSTB4 MODR KSTB5 KSTB6 47Kx4 KSTB7 KSTB8 KSTB9...
  • Page 108 PS-RAM 6/16 SA[0..17] SA[0..17] SD[0..15] SD[0..15] BA[0..8] BA0..BA8 VCC5 VCC5 IC28 IC29 CN19B CN19A SD10 SD11 SD12 FROMBY# FROMBY# FROMBY# SD13 FROMWP# FROMWP# FROMWP# SD14 FROMRP# FROMRP# FROMRP# SD15 FROS2# FROS2# FROS2# FROS1# FROS1# FROS1# SA10 SA10 MROS# MROS# MROS# SA11 SA11 SA12...
  • Page 109 7/16 BA[0..6] SA[0..17] SD[0..15] MEMR# MEMW# FROMWP# FROMRP# FROMBY# IC24 (Socket) IC25 IC30 (Socket) SA10 SA10 SD10 SA11 SA11 SD11 SA10 SD10 DQ10 SA12 SA12 SD12 SA11 SD11 DQ11 VCC5 SA13 SA13 SD13 SA12 SD12 DQ12 SA14 SD14 SA13 SD13 DQ13 SA15 SD15...
  • Page 110 SUPER I/O 8/16 VCC5 VCC5 SA[0..11] SA[0..11] SD[0..7] SD[0..7] R122 R102 R101 R121 R120 VCC5 DTR2# DTR2# CTS2# CTS2# RTS2# RTS2# DSR2# DSR2# DAK#3 TXD2 DAK#3 TXD2 RXD2 0.1U/50V DRQ3 RXD2 DCD2# DCD2# RI2# RI2# DCD1# DCD1# SA10 RI1# RI1# IOCHRDY DTR1# IOCHRDY...
  • Page 111 SLOT 9/16 VCC3 VCC3 R252 IC17B R253 VCC5 IC17C 74LS125 VCC5 74LS125 CHCK# NOWS# R164 VCC5 IOCK- VCC5 10Kx4 10Kx4 R196 C123 330pF R195 R193 R200 R207 10KX3 SD[0..15] SD[0..15] RSTDRV RSTDRV SD[0..15] IRQ9 VCC5 IRQ9 DRQ2 DRQ2 VCC5 R117 -12V NOWS# +12V...
  • Page 112 RS 1 & 2 DRIVER/RECEIVER 10/16 PVCC5 ICPS1.0 R171 100K FB102 R177 R172 RI1# RI1# 3.3K 1.2K C136 BLM31 SW SPDT IC9A 220pF 75189 VCC5 FB120 R115 BLM31 100K C102 +12V 0.1uF R128 R116 FB119 3.3K BLM31 1.2K C108 TXD1 TXD1 220pF FB121...
  • Page 113 RS 3&4 DRIVER/RECEIVER 11/16 VCC5 FB115 R149 BLM31 100K C114 +12V 0.1uF R159 R148 FB114 3.3K BLM31 1.2K C122 TXD2 TXD3 220pF FB116 RXD2 RXD3 BLM31 R147 DTR2# 100K COM3/5 CN DTR3# R158 R146 FB113 DSR2# DSR3# 3.3K 1.2K BLM31 C121 RTS2# RTS3#...
  • Page 114 POLE DISPLAY 12/16 VCC5 FB104 PVCC5 BLM31 C112 +12V 0.1uF TXD8 TXD8 FB105 POLE R137 DTR8# 100K BLM31 DTR8# FB103 R153 R136 DSR8# DSR8# 1.2K 3.3K C116 BLM31 EMJ88HOPL 220pF -12V MC145406...
  • Page 115 MCR I/F 13/16 VCC5 VCC5 (for 4969) R229 R226 R231 R224 R228 R234 MCR CN PVCC5 CN18 4.7KX6 IC18F FB147 R227 FB148 CLS1# CLS1 RDD1# FB149 4069 RCP1# FB150 FB151 CLS2# IC18E RDD2# FB152 R225 RCP2# RDD1 4069 BLM31 5045-0810 IC18D R223 RCP1...
  • Page 116 PARALLEL PORT 14/16 VCC5 VCC5 R178 1Kx4 1Kx4 PP[0..7] CN11 PP[0..7] PSTROB# PAUTOFD# PINIT# PSLCTIN# 53047-1510 MOLEX CN10 PERROR# PACK# PBUSY 53047-1010 MOLEX R104 PSLCT...
  • Page 117 DRAWER 15/16 C66663 VCC5 C66663 DRW CN0 IC4A DRSNS0 DTC114YK 5046-03A R150 C111 0.1uF 6.8K 4AC16 DTA144EK -12V VCC5 C66663 DRW CN1 IC4B DRSNS1 DTC114YK 5046-03A R152 C109 0.1uF 6.8K DTA144EK 4AC16 -12V C66663 R151 R129 DRSNS0 2.7K R130 C110 DRSNS1 |LINK 1000pF...
  • Page 118 POWER 16/16 R131 CN13 VCC5 MLOCK 2SJ187 VFAN IC14 VFAN MLX 53014-0310 PWRGOOD FANON DTC114YK RX5VTXXC C183 R212 0.1u 1.5K -12V VCC5 CN25 C217 47uF/25V 47uF/25V 0.1uF 100uF/10V OS PVCC5 VCC5 C216 0.1uF 3.15A/125V 47uF/25V 47uF/25V -12V PHOLD PHSNS GIL-G-12P-S3T2-E VCC5 VCC5 Q103...
  • Page 119 UP-5700 MAIN PWB LOCATION LIST SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION RS 1&2 DRIVER/RECEIVER VGA CONNECTOR C/BE#1 VGA CONNECTOR VGA CONNECTOR...
  • Page 120 SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION KRTN0 "RTC,MKey,IDE" PS-RAM PSREF PSC2 PS-RAM VGA CONNECTOR "RTC,MKey,IDE" PSREF# PS-RAM PS-RAM PSC2 KRTN1 "RTC,MKey,IDE" VGAC T655550 SUPER I/O PS-RAM...
  • Page 121 SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION SLOT SLOT VCC2 VGA CONNECTOR MCR I/F VGA CONNECTOR SLOT SLOT VGAC T655550 PARALLEL PORT SD11 PSC2 SLOT...
  • Page 122 2. CPU PWB ATCL SA[0..23] SA[0..23] SD[0..15] HD[0..63] SD[0..15] HD[0..63] VFSA VFSB VFSC VFSD VFS5 Interface Interface N N N MMMML L L L L K K K K J J J J J H H H H H G G G G F F F F F E E E E D D D D C C C B B A A A B A B C DAK#[0..7] 2 3 4 1 2 3 4 1 2 3 4 5 1 2 3 4 1 2 3 4 5 1 2 3 4 5 1 2 3 4 1 2 3 4 5 1 2 3 4 1 2 3 4 1 2 3 1 2 1 2...
  • Page 123 CONNECTOR VCC2 150u/6.3V(OS) C/BE#[0..3] C/BE#[0..3] AD[0..31] AD[0..31] C/BE#0 C/BE#1 C/BE#2 C/BE#3 FRAME# FRAME# IRDY# IRDY# TRDY# TRDY# DEVSEL# DEVSEL# STOP# STOP# CPAR CPAR SERR# SERR# AD10 PERR# PERR# AD11 AD12 DBEW# DBEW# AD13 DDRQ DDRQ AD14 DCS3# DCS3# AD15 DCS1# DCS1# DDAK# DDAK#...
  • Page 124 |LINK |ATCL.SCH |CONN.SCH VCC3 VCC5 VCC3 |DRAM.SCH HA[3..31] VCC3 FB16 10u/6.3V(SP) AL35 AK08 A20M# FB13 A20M# A20M# AM34 AJ05 ADS# ADS# ADS# AK32 AHOLD 33*4 AHOLD AHOLD 1000p AN33 AK02 FB14 AL33 AE05 APCHK# AM32 AM02 0.1u ADSC# AK30 FB15 33*4 BE#[0..7] HA10...
  • Page 125 DRAM MD[0..63] MD[0..63] MD[0..63] MD[0..63] MD[0..63] MA[0..11] RMA[0..11] RMA[0..11] RMA[0..11] MA[0..11] MA11 RMA11 MA10 RMA10 BR17 RMA9 22x4 RMA8 MD16 RMA8 I/O0 I/O0 RMA8 RMA9 MD17 RMA9 I/O1 I/O1 RMA0 MD18 RMA0 I/O2 I/O2 RMA7 RMA1 MD19 RMA1 I/O3 I/O3 BR18 RMA6 RMA2...
  • Page 126 UP-5700 CPU PWB LOCATION LIST SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION ATCL ATCL CONNECTOR ATCL ATCL A20M# CPUCLK EADS# CONNECTOR ATCL...
  • Page 127 SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION ATCL ATCL ATCL ATCL ATCL HD34 HD63 LOCK# MD25 MD54 DRAM DRAM ATCL ATCL ATCL ATCL ATCL HD35...
  • Page 128 SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION ATCL ATCL ATCL ATCL RAS#2 VFSA DRAM CONNECTOR ATCL ATCL SBHE# CONNECTOR ATCL REQ3# VFSB ATCL SBHF# ATCL ATCL ATCL TRDY# RESET ATCL...
  • Page 129 3. KEY I/F PWB POS KEY I/F GAE GIL-G-12P-S3T2-E VCC5 VCC5 BLM31 IC4A 74LS125 74HC138 (!ANOTHER BOARD) WMF CN |LINK BLM31 IC4B |TCPANE.SCH 74LS125 |LCD_RLY.SCH |LCD.SCH |LCD2.SCH 74HC138 CLERK CN |MOTHER.SCH |INVERTOR.SCH * IC1/IC2 : 8PIN --- GND MLX 53015-0810 1SS353X7 BLM31 16PIN --- VCC5...
  • Page 130 KEY IF PWB(TOUCH PANEL) VCC5 FB101 AVCC BLM31 BLM31 AVCC VCC5 1SS353 DTA124EKA *PSW0 VCC5 AVCC 1SS353 1SS353 *PSW1 EROMCK EROMSO DTA124EKA EROMSI 0.1uF EROMCS VCC5 1SS353 PSW2 DTC124TKA S-29390AF AVCC AVSS 10KX3 (E PROM) 1SS353 *PSW *RST T/PRES- DTA124EKA *RXINT TXD9 RXD9...
  • Page 131 LCD RELAY I/F CN10 Hsync Vsync to TFT_PANEL PENA PENA SMAD3 04 6214 030 010 800 from VGAC SMAD3 04 6214 030 010 800...
  • Page 132 UP-5700 KEY I/F PWB SIGNAL PAGE PAGE NAME LOCATION SIGNAL PAGE PAGE NAME LOCATION (+)12V POS KEY I/F LCD RELAY I/F AVCC KEY I/F PWB (TOUCH PANEL) LCD RELAY I/F AVCC KEY I/F PWB (TOUCH PANEL) LCD RELAY I/F AVCC...
  • Page 133 4. ISA PWB -12V 22uF/35V IRQ9 AT10 AT10 AT10 AT11 AT11 AT11 AT12 AT12 AT12 AT13 AT13 AT13 AT14 AT14 AT14 AT15 AT15 AT15 AT16 AT16 AT16 AT17 AT17 AT17 AT18 AT18 AT18 AT19 AT19 AT19 AT20 AT20 AT20 AT21 AT21 AT21 AT22...
  • Page 134 UP-5700 ISA PWB SIGNAL PAGE PAGE NAME LOCATION (–)12V ISA PWB ISA PWB ISA PWB VCC5 ISA PWB VCC5 ISA PWB 9 – 38...
  • Page 135 5. INVERTER PWB +12V SHUTDOWN- VR2-1 VR2-2 53015-0510 C101 18pF/3KV 841TN ICP0.5 R104 VLOW COLOR 15.4KF VHIGH BHR-03VS-1 VLOW MONO VHIGH R102 R103 2.2uF/16V C103 M60-04-30-134P 220K 2.2uF/16V MITSUMI 1000pF PGND 0.056uF/100V ICCFL BULB Q101 Q102 ROYER R101 C5001 C5001 100K AGND SHDN...
  • Page 136 6. LCD RELAY PWB LQ10D03J B0...B5 G0...G5 R0...R5 VCC5 VCC5 Hysnc Vsync Hsync Vsync Vsync Hsync CN30 CN31 |LINK |LCD2.SCH...
  • Page 137 SIGNAL PAGE PAGE NAME LOCATION LCD RELAY PWB VCC5 LCD RELAY PWB VCC5 LCD RELAY PWB LCD RELAY PWB LCD RELAY PWB LCD RELAY PWB LCD RELAY PWB LCD RELAY PWB LCD RELAY PWB LCD RELAY PWB LCD RELAY PWB LCD RELAY PWB LCD RELAY PWB LCD RELAY PWB...
  • Page 138 7. POWER SUPPLY PWB 1SS270A +12V FMB26L 5D-11 P1165 +12V 0.01µF 100K D3SB60 104K 630V 330µF SI-3122N (RBV-406) 100µF 820µF 200K 200V PW(PY) (PY)(LXJ) 2200µF/10V PW(PY) 100µF/10V GU(NSN) SBC6-4R7-802 AG01 x 2 PW(PY) 11,12 C30 C31 C32 C33 2200PF ENC112D-10A 2SK2699 250V 104K...

  • Page 139: Chapter 10. Pwb Layout

    CHAPTER 10. PWB LAYOUT 1. UP-5700 Main PWB A side 10 – 1...
  • Page 140 2. UP-5700 CPU PWB A side UP-5700 CPU PWB B side 10 – 2...
  • Page 141 3. UP-5700 KEY I/F PWB A side UP-5700 KEY I/F PWB B side 10 – 3...
  • Page 142 4. UP-5700 ISA PWB A side UP-5700 ISA PWB B side 5. UP-5700 INVERTER PWB A side UP-5700 INVERTER PWB B side 10 – 4...

  • Page 143: Parts Guide

    6. UP-5700 LCD RELAY PWB A side UP-5700 LCD RELAY PWB B side 7. Power supply PWB LAYOUT 7-1. Main PWB For components produced in November and December 1997 Parts side Solder side Apply silicone bond (3490) on the board...
  • Page 144 For components produced in January 1998 and onward Parts side Solder side 10 – 6...
  • Page 145 7-2. Sub PWB Side-A Side-B 10 – 7...
  • Page 146 COPYRIGHT 1997 BY SHARP CORPORATION All rights reserved. Printed in Japan. No part of this publication may be reproduced, stored in a retrieval system, or transmitted. In any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without prior written permission of the publisher.

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