Motorola AltiVec MVME5100 Series Installation & Use Manual page 47

PPCBug Firmware
3
LED/Serial Startup Diagnostic Codes
3-16
ROM Bank A Access Speed (ns) = 80?
This defines the minimum access speed for the Bank A Flash
Device(s) in nanoseconds.
ROM Bank B Access Speed (ns) = 70?
This defines the minimum access speed for the Bank B Flash
Device(s) in nanoseconds.
DRAM Parity Enable [On-Detection/Always/Never - O/A/N] = O?
O
A
N
Note
This parameter also applies to enabling ECC for DRAM.
L2 Cache Parity Enable [On-Detection/Always/Never - O/A/N] = O?
L2 Cache parity is enabled upon detection. (Default)
O
A L2 Cache parity is always enabled.
L2 Cache parity is never enabled.
N
PCI Interrupts Route Control Registers (PIRQ0/1/2/3) = 0A0B0E0F?
Initializes the PIRQx (PCI Interrupts) route control registers in the
IBC (PCI/ISA bus bridge controller). The ENV parameter is a 32-bit
value that is divided by 4 to yield the values for route control registers
PIRQ0/1/2/3. The default is determined by system type.
These codes can be displayed at key points in the initialization of the
hardware devices. The codes are enabled by an ENV parameter.
DRAM parity is enabled upon detection. (Default)
DRAM parity is always enabled.
DRAM parity is never enabled.
Computer Group Literature Center Web Site