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Reset Circuit Pin 69: RES
When the power supply is turned on, first set this pin low and then set it to high. The muting is set to –∞dB and the disk
motor is set to stop.
CLV servo relationship
Muting control
Subcode Q address parameter
Track jump mode
Track count mode
Digital attenuator
OSC
Playback speed
Digital filter normal speed
When the RES pin is low, then the statuses found in the boxes above are set directly.
Other Pins Pin 2: TAI, Pin 16: TEST1, Pin 19: TEST2, Pin 38: TEST3, Pin 40: TEST4, Pin 14: TEST5
These are pins for testing the circuits within the IC. While TAI and TEST2 to TEST5 are equipped with internal pull-
down resistors, for safety reasons, they should be connected to 0 V.
Explanation of the Block Functions
* RAM address control
This IC contains 8 bits × 2K words on on-board RAM, and, depending on the address control, the EFM modulation
data jitter absorption capability can have ±4 frames as the buffer memory capacity. Moreover, normally this buffer
margin is checked, and by precisely controlling the CLV servo circuit PCK-side frequency ratio it is possible to
control the data write address so that it will be centered on the size of the buffer. Also, when the ±4 frame buffer
capacity is exceeded, the write address can be forced to ±0, and because the resulting errors cannot be subjected to
flag processing, the mute is applied for a 128 frame period.
Position
Frequency divider ratio or process
–4 or lower
Forces transition to ±0
–3
589
–2
589
–1
589
±0
588
+1
587
+2
587
+3
587
+4 or greater
Forces transition to ±0
LC78626KE
START
STOP
0 dB
–∞
Address1
Address Free
Conventional
New
Conventional
New
DATA0
DATA 00H to EEH
ON
OFF
Normal speed
Double speed
ON
OFF
Forward frequency division
Standard frequency division
Backwards frequency division
BRAKE
CLV
No. 5995-25/34
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