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Continued from preceding page.
Pin
Pin
I/O
No.
Name
34
CONT3/SBCK
I/O
35
CONT4/SFSY
I/O
36
CONT5/PW
I/O
37
SBSY
O
38
TEST3
I
39
DOUT
O
40
TEST4
I
41
16M/NGJ
O
42
4.2M
O
43
EFLG
O
44
FSX
O
45
EMPH
O
46
C2F
O
47
TOUT
O
48
MR1
I
49
MR2
I
50
TESD
I
51
MUTESL
O
52
LV
P
DD
53
LCHO
AO
54
L/RV
P
SS
55
RCHO
AO
56
RV
P
DD
57
MUTER
O
58
XV
P
DD
59
XOUT
O
60
XIN
I
61
XV
P
SS
62
RWC
I
63
COIN
I
64
CQCK
I
65
SQOUT
O
66
WRQ
O
67
FMT
I
68
EMPP
O
69
RES
I
General I/O pin 3. This controls the commands from the microcontroller. This pin is shared exclusively with
the subcode read clock input (SBCK). When not used, either set this as an input port and connect to 0 V, or
set this as an output port and leave it open.
General I/O pin 4. This controls the commands from the microcontroller. This pin is shared exclusively with
the subcode frame sync signal output (SFSY). When not used, either set this as an input port and connect
to 0 V, or set this as an output port and leave it open.
General I/O pin 5. This controls the commands from the microcontroller. This pin is shared, exclusively, with
the subcode P, Q, R, S, T, U, V, W output (PW). When not used, either set this as an input port and connect
to 0 V, or set this as an output port and leave it open.
Subcode block sync signal output
Test input. Equipped with an internal pull-down resistor. Must be connected to 0 V.
Digital output. EIAJ format.
Test input. Equipped with an internal pull-down resistor. Must be connected to 0 V.
Shared function pin that functions either as the 16.9344 MHz output (16M) or as the C2 flag data continuity check
start signal (detection start is indicated by a low to high transition). Controlled by microcontroller commands.
4.2336 MHz output
C1, C2, one error, two error error correction monitor output
7.35 kHz sync signal output (frequency divided from the crystal oscillator).
Deemphasis monitor output. When high level, a deemphasis disk is being played back.
C2 flag output
Test output. Under normal operation, this should be left open.
DRAM switch: high : 1M, low : 4M
1 M: high, low 4 M: low, low 16 M: low, high 4 M X 2: high, high (MR1, MR2)
Test input. Must be connected to 0V.
L channel mute output
L channel power supply
L channel output
For the one-bit D/A
L/R channel ground. Must be connected to 0 V.
converter
R channel output
R channel power supply
R channel mute output
Crystal oscillator power supply
16.9344 MHz crystal oscillator connection
Crystal oscillator ground. Must be connected to 0 V.
Read/write control input. Schmidt input.
Microcontroller command input
Input pin for the command input latch clock and the subcode readout clock. Schmitt input.
Subcode Q output
Subcode Q output standby output
Operating mode switch: high: shock proof, low: through.
DRAM empty (an RZP pulse is output when the DRAM is empty).
External reset input: low reset (all internal blocks are reinitialized).
LC78626KE
Description
Output pin states
during reset
Input mode
Input mode
Input mode
Undefined
—
Undefined
—
Clock output
Clock output
Undefined
Undefined
Low-level output
Undefined
Undefined
—
—
High-level output
—
—
—
—
—
High-level output
—
—
—
—
—
—
Undefined
Undefined
—
Low-level output
—
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No. 5995-9/34
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