Epson S1C17M01 Technical Manual
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Epson S1C17M01 Technical Manual

Epson S1C17M01 Technical Manual

Cmos 16-bit single chip microcontroller
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CMOS 16-BIT SINGLE CHIP MICROCONTROLLER
S1C17M01
Technical Manual
Rev. 1.2

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Summary of Contents for Epson S1C17M01

  • Page 1 CMOS 16-BIT SINGLE CHIP MICROCONTROLLER S1C17M01 Technical Manual Rev. 1.2...
  • Page 2 2. This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a consumer product. The user should use it properly and in a safe manner. Seiko Epson dose not assume any responsibility or liability of any kind of damage and/or fire coursed by the use of it.

  • Page 3: Notational Conventions And Symbols In This Manual

    PREFACE Preface This is a technical manual for designers and programmers who develop a product using the S1C17M01. This document describes the functions of the IC, embedded peripheral circuit operations, and their control methods. For the CPU functions and instructions, refer to the “S1C17 Family S1C17 Core Manual.” For the functions and operations of the debugging tools, refer to the respective tool manuals.

  • Page 4: Table Of Contents

    3.2.4 I/O Area Reserved for the S1C17 Core ............3-2 3.3 Debugger ........................3-2 3.3.1 Debugging Functions..................3-2 3.3.2 Resource Requirements and Debugging Tools ..........3-3 3.3.3 List of debugger input/output pins ..............3-3 3.3.4 External Connection ..................3-3 Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 5 6.3.2 Clock Supply in SLEEP Mode ................6-3 6.3.3 Clock Supply in DEBUG Mode ................. 6-3 6.4 Operations ........................6-3 6.4.1 Initialization ....................... 6-3 6.4.2 Port Input/Output Control ................. 6-5 6.5 Interrupts ......................... 6-6 Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 6 RTC Hour/Minute Alarm Register ....................8-8 RTC Stopwatch Control Register ....................8-8 RTC Second/1Hz Register ......................8-9 RTC Hour/Minute Register ....................... 8-10 RTC Month/Day Register ......................8-11 RTC Year/Week Register ......................8-11 Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 7 11.2 Input/Output Pins and External Connections .............. 11-2 11.2.1 List of Input/Output Pins ................11-2 11.2.2 External Connections ..................11-2 11.2.3 Input Pin Pull-Up Function................11-2 11.2.4 Output Pin Open-Drain Output Function ............11-2 Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 8 SPIA Ch.n Control Register ..................... 12-12 SPIA Ch.n Transmit Data Register ..................12-13 SPIA Ch.n Receive Data Register ................... 12-13 SPIA Ch.n Interrupt Flag Register ................... 12-13 SPIA Ch.n Interrupt Enable Register ..................12-14 Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 9 14.4.6 LCD Contrast Adjustment ................14-5 14.5 Operations ........................14-5 14.5.1 Initialization ....................14-5 14.5.2 Display On/Off ....................14-6 14.5.3 Inverted Display ..................... 14-6 14.5.4 Drive Duty Switching ..................14-6 14.5.5 Drive Waveforms .................... 14-7 Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 10 16.3.2 Clock Supply in SLEEP Mode ............... 16-3 16.3.3 Clock Supply in DEBUG Mode ..............16-3 16.4 Operations ........................16-3 16.4.1 Initialization ....................16-3 16.4.2 Measurement Control and Operations ............16-4 16.4.3 Pulse Output Function ................... 16-6 Seiko Epson Corporation viii S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 11 0x43c0–0x43d2 I C (I2C) ..................AP-A-12 0x5100–0x510c 16-bit Timer (T16) Ch.2............... AP-A-13 0x5120–0x512c 16-bit Timer (T16) Ch.3............... AP-A-13 0x5260–0x526c 16-bit Timer (T16) Ch.4............... AP-A-14 0x5270–0x527a Synchronous Serial Interface (SPIA) Ch.1 ........AP-A-14 Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 12 B.1 Operating Status Configuration Examples for Power Saving ........AP-B-1 B.2 Other Power Saving Methods ..................AP-B-2 Appendix C Mounting Precautions ................AP-C-1 Appendix D Measures Against Noise ................ AP-D-1 Appendix E Initialization Routine ................AP-E-1 Revision History Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 13: Overview

    1 OVERVIEW 1 Overview The S1C17M01 is an ultra low-power MCU equipped with an MR (magnetoresistive) sensor controller that al- lows an MR sensor array optimized for flow measurement (recommended sensor: KG1205-61 manufactured by KOHDEN Co., Ltd.) to be connected directly. This IC includes an LCD driver to display the flow count and the...
  • Page 14 IOSC = ON, OSC1 = 32 kHz, RTC = ON, CPU = IOSC, LCD = OFF (no panel load) Shipping form QFP13-64PIN (P-LQFP064-1010-0.50, 10 × 10 mm, t = 1.7 mm, 0.5 mm pitch) Die form (Pad pitch: 100 µm) *1 Shown in parentheses is a JEITA package name. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 15: Block Diagram

    Display RAM 16-bit timer 8 bit 32 bytes (T16) EXCL0–1 5 Ch. CMPIN0–1P MR sensor CMPIN0–1N Power generator UART USIN0 controller EVPLS (PWG) (UART) USOUT0 (AMRC) SENSEN EXHYS0–1 Figure 1.2.1 S1C17M01 Block Diagram Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 16: Pins

    SEG25 OSC2 OSC2 SEG24 P00/EXOSC/RFCLKO0/SEG0 SEG23 P01/LFRO/USIN0/SEG1 SEG22 SEG21 P02/RTC1S/USOUT0/SEG2 P03/SCL0/SENB0 #SPISS1/SEG20 P04/SDA0/SENA0 SPICLK1/SEG19 P05/SDI0/REF0 SDO1/SEG18 P06/SDO0/RFIN0 SDI1/SEG17 P07/SPICLK0/EVPLS/EXSVD FOUT/SEG16 SDI0/SCL0/SEG3 EXCL1/SEG15 SDO0/SDA0/SEG4 SPICLK0/EXHYS1/SEG5 #SPISS0/EXHYS0/SEG6 Figure 1.3.1.1 S1C17M01 Pin Configuration Diagram (TQFP13-64PIN) Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 17: Pad Configuration Diagram (Chip)

    SDO0/SDA0/SEG4 SPICLK0/EXHYS1/SEG5 #SPISS0/EXHYS0/SEG6 2.446 mm Figure 1.3.2.1 S1C17M01 Pad Configuration Diagram (Chip) Pad opening No. 1–16, 33–48: X = 76 µm, Y = 90 µm No. 17–32, 49–64: X = 90 µm, Y = 76 µm Chip thickness 400 µm Table 1.3.2.1 Pad Coordinates...

  • Page 18: Pin Descriptions

    Synchronous serial interface Ch.0 data output RFIN0 R/F converter Ch.0 oscillation input – Hi-Z I/O port SPICLK0 Synchronous serial interface Ch.0 clock input/output EVPLS MR sensor controller pulse output EXSVD External power supply voltage detection input Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 19 LCD segment output – Hi-Z Hi-Z – ✓ FOUT Clock external output SEG16 LCD segment output – Hi-Z Hi-Z – ✓ SDI1 Synchronous serial interface Ch.1 data input SEG17 LCD segment output Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 20 OSC1 OSC1 – – OSC1 oscillator circuit input OSC2 OSC2 – – OSC1 oscillator circuit output Note: In the peripheral circuit descriptions, the assigned signal name is used as the pin name. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 21: Power Supply, Reset, And Clocks

    SLEEP mode (when all oscillators are stopped, or OSC1 only is active) When a clock source except for OSC1 is active HALT mode (when OSC1 only is active) RUN mode (when OSC1 only is active) Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 22: System Reset Controller (Src)

    #RESET pin, so the pin can be left open. For the #RESET pin characteris- tics, refer to “#RESET pin characteristics” in the “Electrical Characteristics” chapter. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 23: Reset Sources

    • IOSCCLK output from the IOSC oscillator circuit is used as the boot clock for fast booting. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 24: Input/Output Pins

    2.3.3 Clock Sources IOSC oscillator circuit The IOSC oscillator circuit features a fast startup and no external parts are required for oscillating. Figure 2.3.3.1 shows the configuration of the IOSC oscillator circuit. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 25 EXOSC clock input EXOSC is an external clock input circuit that supports square wave and sine wave clocks. Figure 2.3.3.3 shows the configuration of the EXOSC clock input circuit. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 26: Operations

    Furthermore, the oscillation start time being actually reduced depends on the characteristics of the resonator used. Figure 2.3.4.2 shows an operation example when the oscillation start- up control circuit is used. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 27 0x0096 to the MSCPROT.PROT[15:0] bits before the register setting can be altered. For the transition between the operating modes including the system clock switching, refer to “Operating Mode.” Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 28 CLGSCLK.CLKSRC[1:0] = 0x1 (OSC1) CLGSCLK.CLKSRC[1:0] = 0x0 (IOSC) CLGSCLK.WUPSRC[1:0] = 0x0 (IOSC) CLGSCLK.WUPSRC[1:0] = 0x0 (IOSC) ∗ Switching to IOSC that features fast initiation allows high-speed processing. Figure 2.3.4.4 Clock Control Example at SLEEP Cancelation Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 29 7. The OSC1 oscillation stops if the CLGINTF.OSC1STPIF bit = 1 after an interrupt occurs. If the CLGOSC1.OSDRB bit = 1, the hardware restarts the OSC1 oscillator circuit. Note: Enabling the oscillation stop detection function increase the oscillation stop detector current OSD1 Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 30: Operating Mode

    When a debug interrupt occurs, the CPU enters DEBUG mode. DEBUG mode is canceled when the retd in- struction is executed. For more information on DEBUG mode, refer to “Debugger” in the “CPU and Debugger” chapter. Seiko Epson Corporation 2-10 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 31: Interrupts

    For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 2-11 (Rev. 1.2)

  • Page 32: Control Registers

    CLKSRC[1:0] bits and the CLGSCLK.CLKDIV[1:0] bits, respectively. If the same clock source and division ratio as those that are configured before placing the IC into SLEEP mode are used at wake-up, set the CLKSCLK.WUPMD bit to 0. Bit 14 Reserved Seiko Epson Corporation 2-12 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 33: Clg Oscillation Control Register

    CLG Oscillation Control Register Register name Bit name Initial Reset Remarks CLGOSC 15–12 – – – EXOSCSLPC – – OSC1SLPC IOSCSLPC 7–4 – – EXOSCEN – – OSC1EN IOSCEN Bits 15–12 Reserved Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 2-13 (Rev. 1.2)

  • Page 34: Clg Iosc Control Register

    • The auto-trimming function does not work if the OSC1 oscillator circuit is stopped. Make sure the CLGINTF.OSC1STAIF bit is set to 1 before starting the trimming operation. Bits 3–0 Reserved Seiko Epson Corporation 2-14 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 35: Clg Osc1 Control Register

    For more information, refer to “OSC1 oscillator circuit characteristics, Internal gate capacitance C ” in the “Electrical Characteristics” chapter. Bits 7–6 INV1B[1:0] These bits set the oscillation inverter gain that will be applied at boost startup of the OSC1 oscillator circuit. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 2-15 (Rev. 1.2)

  • Page 36: Clg Interrupt Flag Register

    1 (W): Clear flag 0 (W): Ineffective Each bit corresponds to the interrupt as follows: CLGINTF.OSC1STPIF bit: OSC1 oscillation stop interrupt CLGINTF.IOSCTEDIF bit: IOSC oscillation auto-trimming completion interrupt Bits 3–2 Reserved Seiko Epson Corporation 2-16 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 37: Clg Interrupt Enable Register

    CLGINTE.IOSCSTAIE bit: IOSC oscillator circuit CLG FOUT Control Register Register name Bit name Initial Reset Remarks CLGFOUT 15–8 – 0x00 – – – – 6–4 FOUTDIV[2:0] 3–2 FOUTSRC[1:0] – – FOUTEN Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 2-17 (Rev. 1.2)
  • Page 38 0 (R/W): Disable external output Note: Since the FOUT signal generated is out of sync with writings to the CLGFOUT.FOUTEN bit, a glitch may occur when the FOUT output is enabled or disabled. Seiko Epson Corporation 2-18 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 39: Cpu And Debugger

    3 CPU AND DEBUGGER 3 CPU and Debugger 3.1 Overview This IC incorporates the Seiko Epson original 16-bit CPU core (S1C17) with a debugger. The main features of the CPU core are listed below. • Seiko Epson original 16-bit RISC processor...

  • Page 40: Cpu Core

    DBRUN bit, refer to “Clock Supply in DEBUG Mode” in each peripheral circuit chapter. DE- BUG mode continues until a cancel command is sent from the personal computer or the CPU executes the retd in- struction. Neither hardware interrupts nor NMI are accepted during DEBUG mode. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 41: Resource Requirements And Debugging Tools

    For the recommended pull-up resistor value, refer to “Recommended Operating Conditions, DSIO pull-up resis- tor R ” in the “Electrical Characteristics” chapter. R is not required when using the DSIO pin as a general- purpose I/O port pin. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 42: Control Register

    – 23–0 DBRAM[23:0] *1 Debugging work area start address Bits 31–24 Reserved Bits 23–0 DBRAM[23:0] The start address of the debugging work area (64 bytes) can be read out with these bits. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 43: Memory And Bus

    Access size designated by the CPU instructions (e.g., ld %rd, [%rb] → 16-bit data transfer) Table 4.2.1 lists numbers of bus access cycles by different device size and access size. The peripheral circuits can be accessed with an 8-bit, 16-bit, or 32-bit instruction. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 44: Flash Memory

    The number of bus access cycles for reading can be configured using the FLASHCWAIT.RDWAIT[1:0] bits. Select a setting for higher frequency than the system clock. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 45: Flash Programming

    Note: The 64 bytes at the end of the RAM is reserved as the debug RAM area. When using the debug functions under application development, do not access this area from the application program. This area can be used for applications of mass-produced devices that do not need debugging. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 46: Display Data Ram

    SVD Control Register 0x4104 SVDINTF SVD Status and Interrupt Flag Register 0x4106 SVDINTE SVD Interrupt Enable Register 16-bit timer (T16) Ch.0 0x4160 T16_0CLK T16 Ch.0 Clock Control Register 0x4162 T16_0MOD T16 Ch.0 Mode Register Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 47 T16 Ch.1 Control Register 0x43a6 T16_1TR T16 Ch.1 Reload Data Register 0x43a8 T16_1TC T16 Ch.1 Counter Data Register 0x43aa T16_1INTF T16 Ch.1 Interrupt Flag Register 0x43ac T16_1INTE T16 Ch.1 Interrupt Enable Register Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 48 0x544a RFC0TCL RFC Ch.0 Time Base Counter Low Register 0x544c RFC0TCH RFC Ch.0 Time Base Counter High Register 0x544e RFC0INTF RFC Ch.0 Interrupt Flag Register 0x5450 RFC0INTE RFC Ch.0 Interrupt Enable Register Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 49: System-Protect Function

    R/WP Always set to 0. – – – 6–4 (reserved) – – – 2–0 IRAMSZ[2:0] R/WP Bits 15–3 Reserved Bits 2–0 IRAMSZ[2:0] These bits set the internal RAM size that can be used. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 50: Flashc Flash Read Cycle Register

    FLASHCWAIT.RDWAIT[1:0] bits Number of bus Access cycles System clock frequency 16.3 MHz (max.) 16.3 MHz (max.) 16.3 MHz (max.) 8.2 MHz (max.) Note: Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 51: Interrupt Controller (Itc)

    TTBR + 0x04 Address misaligned interrupt Memory access instruction – (0xfffc00) Debugging interrupt brk instruction, etc. 2 (0x02) TTBR + 0x08 – 3 (0x03) TTBR + 0x0c Reserved for C compiler – – Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 52: Vector Table Base Address (Ttbr)

    Bits 7 to 0 in the MSCTTBRL register are fixed at 0, so the vector table always begins from a 256-byte boundary address. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 53: Initialization

    The previously occurring interrupt is held. The held interrupt is canceled and no interrupt is generated if the interrupt flag in the peripheral circuit is cleared via software. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 54: Conditions To Accept Interrupt Requests By The Cpu

    Note: When HALT or SLEEP mode is canceled, the CPU jumps to the interrupt handler routine after executing one instruction. To execute the interrupt handler routine immediately after wake-up, place the nop instruction at just behind the halt/slp instruction. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 55: Control Registers

    Clock generator interrupt (ILVCLG) ITCLV2 15–11 – 0x00 – – (ITC Interrupt Level 10–8 ILV5[2:0] UART interrupt (ILVUART_0) Setup Register 2) 7–3 – 0x00 – – 2–0 ILV4[2:0] 16-bit timer Ch.0 interrupt (ILVT16_0) Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 56 (ILVSPIA_1) ITCLV7 15–11 – 0x00 – – (ITC Interrupt Level 10–8 ILV15[2:0] MR sensor controller interrupt Setup Register 7) (ILVAMRC) 7–3 – 0x00 – – 2–0 ILV14[2:0] R/F converter interrupt (ILVRFC_0) Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 57: O Ports (Pport)

    Input signal filter Interrupt PxEDGEy control circuit PxINT PxIFy PxIEy Interrupt controller CLK_PPORT CLKSRC[1:0] Clock CLKDIV[3:0] generator DBRUN Exist only in the ports that supports the interrupt function. Figure 6.1.1 PPORT Configuration Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 58: I/O Cell Structure And Functions

    Falling time (port level = high → low) [second] High level Schmitt input threshold voltage [V] Low level Schmitt input threshold voltage [V] : Pull-up/pull-down resistance [W] Pin capacitance [F] Parasitic capacitance on the board [F] BOARD Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 59: Cmos Output And High Impedance State

    • Port pins: High impedance state • Port function: Configured to GPIO This status continues until the ports are configured via software. The debugging function ports are configured for debug signal input/output. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 60 * Steps 1 and 5 are required for the ports with an interrupt function. Step 2 is required for the ports with a chat- tering filter function. Table 6.4.1.1 lists the port status according to the combination of data input/output control and pull-up/down control. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 61: Port Input/Output Control

    SLEEP mode. If CLK_PPORT is configured to stop in SLEEP mode, PPORT inactivates the chattering filter during SLEEP mode to input pin status transitions directly to itself. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 62: Interrupts

    These bits do not affect the outputs when the port is used as a peripheral I/O function. Bits 7–0 PxIN[7:0] The GPIO port pin status can be read out from these bits. 1 (R): Port pin = High level 0 (R): Port pin = Low level Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 63: Px Port Enable Register

    – 7–0 PxIF[7:0] 0x00 Cleared by writing 1. *1: This register is effective when the GPIO function is selected. *2: The bit configuration differs depending on the port group. Bits 15–8 Reserved Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 64: Px Port Interrupt Control Register

    Bits 15–8 Reserved Bits 7–0 PxSEL[7:0] These bits select whether each port is used for the GPIO function or a peripheral I/O function. 1 (R/W): Use peripheral I/O function 0 (R/W): Use GPIO function Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 65: Px Port Function Select Register

    The PPORT operating clock should be configured by selecting the clock source using the PCLK. CLKSRC[1:0] bits and the clock division ratio using the PCLK.CLKDIV[3:0] bits as shown in Table 6.6.2. These settings determine the input sampling time of the chattering filter. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 66: P Port Interrupt Flag Group Register

    A port generated an interrupt 0 (R): No port generated an interrupt The PINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt is cleared. Seiko Epson Corporation 6-10 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 67: Control Register And Port Function Configuration Of This Ic

    – SDA0 SENA0 – – – – SPIA Ch.0 SDI0 REF0 – – – – SPIA Ch.0 SDO0 RFIN0 – – – – SPIA Ch.0 SPICLK0 AMRC EVPLS EXSVD – – Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 6-11 (Rev. 1.2)

  • Page 68: P1 Port Group

    Table 6.7.3.1 Control Registers for P2 Port Group Register name Bit name Initial Reset Remarks P2DAT 15–10 – 0x00 – – (P2 Port Data 9–8 P2OUT[1:0] Register) 7–2 – 0x00 – 1–0 P2IN[1:0] Seiko Epson Corporation 6-12 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 69: P3 Port Group

    15–8 – 0x00 – – (P3 Port Chattering 7–2 – 0x00 – Filter Enable Register) 1–0 P3CHATEN[1:0] P3MODSEL 15–8 – 0x00 – – (P3 Port Mode Select 7–0 P3SEL[7:0] 0x00 Register) Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 6-13 (Rev. 1.2)

  • Page 70: P4 Port Group

    – – LCD8A SEG26 – – – – – – – LCD8A SEG27 – – – – – – – LCD8A SEG28/COM7 – – – – – – – LCD8A SEG29/COM6 Seiko Epson Corporation 6-14 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 71: P5 Port Group

    – – – – LCD8A COM1 – – – – – – – LCD8A COM0 – – – – – – – – – – – – – – – – Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 6-15 (Rev. 1.2)

  • Page 72: Pd Port Group

    R/WP Register) 7–4 CLKDIV[3:0] R/WP 3–2 – – 1–0 CLKSRC[1:0] R/WP PINTFGRP 15–8 – 0x00 – – (P Port Interrupt Flag 7–6 – – Group Register) P5INT 4–1 – – P0INT Seiko Epson Corporation 6-16 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 73: Watchdog Timer (Wdt)

    = — — — — — — — — (Eq. 7.1) CLK_WDT Where Counter overflow cycle [second] CLK_WDT: WDT operating clock frequency [Hz] Example) = 4 seconds when CLK_WDT = 256 Hz Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 74: Clock Supply In Debug Mode

    If the clock source stops in SLEEP mode, WDT stops. To prevent generation of an unnecessary reset after clearing SLEEP mode, reset WDT before executing the slp instruction. WDT should also be stopped as required using the WDTCTL.WDTRUN[3:0] bits. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 75: Control Registers

    WDTCNTRST Always read as 0. 3–0 WDTRUN[3:0] R/WP – Bits 15–5 Reserved Bit 4 WDTCNTRST This bit resets WDT. 1 (WP): Reset 0 (WP): Ignored 0 (R): Always 0 when being read Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 76 Always 0x0 is read if a value other than 0xa is written. Since a reset may be generated immediately after running depending on the counter value, WDT should also be reset concurrently when running WDT. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 77: Real-Time Clock (Rtca)

    * Indicates the status when the pin is configured for RTCA. If the port is shared with the RTCA output function and other functions, the RTCA function must be assigned to the port. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 78: Clock Settings

    · · · · · · · · · · · · · · · 0x3e 59.1 0x7e -1.9 0x3f 60.1 0x7f -1.0 Minimum resolution: 1 ppm, Correction rate range: -61.0 to 60.1 ppm Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 79: Operations

    3. Write 1 to the RTCINTF.ALARMIF bit to clear the alarm interrupt flag. 4. Write 1 to the RTCINTE.ALARMIE bit to enable alarm interrupts. When the real-time clock counter reaches the alarm time set in Step 2, an alarm interrupt occurs. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 80: Real-Time Clock Counter Operations

    8.4.4 Stopwatch Count-up Pattern The stopwatch consists of 1/100-second and 1/10-second counters and these counters perform counting up in incre- ments of approximate 1/100 and 1/10 seconds with the count-up patterns shown in Figure 8.4.4.1. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 81: Interrupts

    1 Hz counter value. • An alarm interrupt occurs after a lapse of 1/256 second from matching between the AM/PM (in 12H mode), hour, minute, and second counter value and the alarm setting value. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 82: Control Registers

    Depending on these operation timings, the +1 second correction may be executed after the count-up operation resumes. For more information on the +1 second correction, refer to “Real-Time Clock Counter Operations.” Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 83: Rtc Second Alarm Register

    The RTCALM1.RTCSHA[2:0] bits and the RTCALM1.RTCSLA[3:0] bits set the 10-second digit and 1-second digit of the alarm time, respectively. A value within 0 to 59 seconds can be set in BCD code as shown in Table 8.6.1. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 84: Rtc Hour/Minute Alarm Register

    SWRUN Bits 15–12 BCD10[3:0] Bits 11–8 BCD100[3:0] The 1/10-second and 1/100-second digits of the stopwatch counter can be read as a BCD code from the RTCSWCTL.BCD10[3:0] bits and the RTCSWCTL.BCD100[3:0] bits, respectively. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 85: Rtc Second/1Hz Register

    1-second digit of the second counter, respectively. The setting/read values are a BCD code within the range from 0 to 59. Note: Be sure to avoid writing to the RTCSEC.RTCSH[2:0]/RTCSL[3:0] bits while the RTCCTL. RTCBSY bit = 1. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 86: Rtc Hour/Minute Register

    1 to 12 in 12H mode or 0 to 23 in 24H mode. Note: Be sure to avoid writing to the RTCHUR.RTCHH[1:0]/RTCHL[3:0] bits while the RTCCTL. RTCBSY bit = 1. Bit 7 Reserved Seiko Epson Corporation 8-10 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 87: Rtc Month/Day Register

    The day of the week counter is a base-7 counter and the setting/read values are 0x0 to 0x6. Table 8.6.2 lists the correspondence between the count value and day of the week. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 8-11 (Rev. 1.2)

  • Page 88: Rtc Interrupt Flag Register

    The following shows the correspondence between the bit and interrupt: RTCINTF.RTCTRMIF bit: Theoretical regulation completion interrupt RTCINTF.SW1IF bit: Stopwatch 1 Hz interrupt RTCINTF.SW10IF bit: Stopwatch 10 Hz interrupt RTCINTF.SW100IF bit: Stopwatch 100 Hz interrupt Bits 11–9 Reserved Seiko Epson Corporation 8-12 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 89: Rtc Interrupt Enable Register

    The following shows the correspondence between the bit and interrupt: RTCINTE.RTCTRMIE bit: Theoretical regulation completion interrupt RTCINTE.SW1IE bit: Stopwatch 1 Hz interrupt RTCINTE.SW10IE bit: Stopwatch 10 Hz interrupt RTCINTE.SW100IE bit: Stopwatch 100 Hz interrupt Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 8-13 (Rev. 1.2)
  • Page 90 RTCINTE.1DAYIE bit: 1-day interrupt RTCINTE.1HURIE bit: 1-hour interrupt RTCINTE.1MINIE bit: 1-minute interrupt RTCINTE.1SECIE bit: 1-second interrupt RTCINTE.1_2SECIE bit: 1/2-second interrupt RTCINTE.1_4SECIE bit: 1/4-second interrupt RTCINTE.1_8SECIE bit: 1/8-second interrupt RTCINTE.1_32SECIE bit: 1/32-second interrupt Seiko Epson Corporation 8-14 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 91: Supply Voltage Detector (Svd)

    Clock generator CLKDIV[2:0] DBRUN SVDC[4:0] EXSVD Voltage VDSEL comparator SVDDT circuit Detection SVDSC[1:0] SVDIF result counter SVDIE SVDRE[3:0] Interrupt/reset To system reset circuit control circuit To interrupt controller Figure 9.1.1 SVD Configuration Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 92: Input Pin And External Connection

    SLEEP mode and SVD stops with the register settings maintained at those before entering SLEEP mode. After the CPU returns to normal mode, CLK_SVD is supplied and the SVD operation resumes. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 93: Clock Supply In Debug Mode

    SVDCTL.MODEN bit = 1, wait for at least SVD circuit response time before reading the SVDINTF.SVDDT bit (refer to “Supply Voltage Detector Characteristics, SVD circuit response time t ” in the “Electrical Char- acteristics” chapter). Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 94: Svd Operations

    SVDIF bit). An interrupt request is sent to the interrupt controller only when the SVDINTF.SVDIF bit is set while the interrupt is enabled by the SVDINTE.SVDIE bit. For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 95: Svd Reset

    0 (R/WP): No clock supplied in DEBUG mode Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the SVD operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of SVD. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 96: Svd Control Register

    SVD detection voltage V 0x1f High 0x1e ↑ 0x0d ↓ 0x0c 0x0b–0x00 Use prohibited For more information, refer to “Supply Voltage Detector Characteristics, SVD detection voltage ” in the “Electrical Characteristics” chapter. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 97: Svd Status And Interrupt Flag Register

    This bit indicates the low power supply voltage detection interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 98: Svd Interrupt Enable Register

    Notes: • If the SVDCTL.SVDRE[3:0] bits are set to 0xa, no low power supply voltage detection in- terrupt will occur, as a reset is issued at the same timing as an interrupt. • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 99: 16-Bit Timers (T16)

    If the port is shared with the EXCLm pin and other functions, the EXCLm input function must be assigned to the port before using the event counter function. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 10-1 (Rev. 1.2)

  • Page 100: Clock Settings

    (Set reload data (counter preset data)) 5. Set the following bits when using the interrupt: - Write 1 to the T16_nINTF.UFIF bit. (Clear interrupt flag) - Set the T16_nINTE.UFIE bit to 1. (Enable underflow interrupt) Seiko Epson Corporation 10-2 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 101: Counter Underflow

    At the same time the counter stops, the T16_ nCTL.PRUN bit is cleared automatically. Select this mode to stop the counter after an interrupt has occurred once, such as for checking a specific lapse of time. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 10-3 (Rev. 1.2)

  • Page 102: Counter Value Read

    Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the T16 Ch.n operating clock (counter clock). Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of T16 Ch.n. Seiko Epson Corporation 10-4 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 103: T16 Ch.n Mode Register

    PRESET MODEN Bits 15–9 Reserved Bit 8 PRUN This bit starts/stops the timer. 1 (W): Start timer 0 (W): Stop timer 1 (R): Timer is running 0 (R): Timer is idle Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 10-5 (Rev. 1.2)

  • Page 104: T16 Ch.n Reload Data Register

    The current counter value can be read out from these bits. T16 Ch.n Interrupt Flag Register Register name Bit name Initial Reset Remarks T16_nINTF 15–8 – 0x00 – – 7–1 – 0x00 – UFIF Cleared by writing 1. Bits 15–1 Reserved Seiko Epson Corporation 10-6 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 105: T16 Ch.n Interrupt Enable Register

    This bit enables T16 Ch.n underflow interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 10-7 (Rev. 1.2)

  • Page 106: Uart (Uart)

    Shift register RZI modulator USOUTn TXD[7:0] INVIRTX IRMD Interrupt OUTMD controller TENDIE TENDIF FEIE FEIF Interrupt PEIE PEIF control circuit OEIE OEIF RB2FIE RB2FIF RB1FIE RB1FIF TBEIE TBEIF Figure 11.1.1 UART Configuration Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 11-1 (Rev. 1.2)

  • Page 107: Input/Output Pins And External Connections

    When using the UART during SLEEP mode, the UART operating clock CLK_UARTn must be configured so that it will keep supplying by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_UARTn clock source. Seiko Epson Corporation 11-2 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 108: Clock Supply In Debug Mode

    (UAnMOD.STPB bit = 1). Parity function The parity function is configured using the UAnMOD.PREN and UAnMOD.PRMD bits. Table 11.4.1 Parity Function Setting UAnMOD.PREN bit UAnMOD.PRMD bit Parity function Odd parity Even parity Non parity Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 11-3 (Rev. 1.2)

  • Page 109: Operations

    2. Write transmit data to the UAnTXD register. 3. Wait for a UART interrupt when using the interrupt. 4. Repeat Steps 1 to 3 (or 1 and 2) until the end of transmit data. Seiko Epson Corporation 11-4 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 110: Data Reception

    2. Check to see if the UAnINTF.RB1FIF bit is set to 1 (receive buffer one byte full). 3. Read the received data from the UAnRXD register. 4. Repeat Steps 1 to 3 (or 2 and 3) until the end of data reception. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 11-5 (Rev. 1.2)

  • Page 111: Irda Interface

    Set the UAnMOD.IRMD bit to 1 to use the IrDA interface. Data transfer control is identical to that for normal interface even if the IrDA interface function is enabled. Seiko Epson Corporation 11-6 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 112: Receive Errors

    Note, however, that the set timing depends on the buffer status at that point. • When the receive data buffer is empty The interrupt flag will be set when the data that encountered an error is transferred to the re- ceive data buffer. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 11-7 (Rev. 1.2)

  • Page 113: Parity Error

    11.8 Control Registers UART Ch.n Clock Control Register Register name Bit name Initial Reset Remarks UAnCLK 15–9 – 0x00 – – DBRUN 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation 11-8 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 114: Uart Ch.n Mode Register

    1 (R/W): Enable output inverting function 0 (R/W): Disable output inverting function Bit 7 Reserved Bit 6 PUEN This bit enables pull-up of the USINn pin. 1 (R/W): Enable pull-up 0 (R/W): Disable pull-up Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 11-9 (Rev. 1.2)

  • Page 115: Uart Ch.n Baud-Rate Register

    Note: The UAnBR register settings can be altered only when the UAnCTL.MODEN bit = 0. UART Ch.n Control Register Register name Bit name Initial Reset Remarks UAnCTL 15–8 – 0x00 – – 7–2 – 0x00 – SFTRST MODEN Bits 15–2 Reserved Seiko Epson Corporation 11-10 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 116: Uart Ch.n Transmit Data Register

    PEIF H0/S0 OEIF H0/S0 Cleared by writing 1. RB2FIF H0/S0 Cleared by reading the UAnRXD reg- ister. RB1FIF H0/S0 TBEIF H0/S0 Cleared by writing to the UAnTXD register. Bits 15–10 Reserved Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 11-11 (Rev. 1.2)

  • Page 117: Uart Ch.n Interrupt Enable Register

    Bit 5 FEIE Bit 4 PEIE Bit 3 OEIE Bit 2 RB2FIE Bit 1 RB1FIE Bit 0 TBEIE These bits enable UART interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Seiko Epson Corporation 11-12 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 118 UAnINTE.PEIE bit: Parity error interrupt UAnINTE.OEIE bit: Overrun error interrupt UAnINTE.RB2FIE bit: Receive buffer two bytes full interrupt UAnINTE.RB1FIE bit: Receive buffer one byte full interrupt UAnINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 11-13 (Rev. 1.2)

  • Page 119: Synchronous Serial Interface (Spia)

    SFTRST RXD[15:0] LSBFST CPHA SPICLKn CPOL Pull-up/down control PUEN circuit (Used only in slave mode) #SPISSn Interrupt controller Interrupt TENDIE TENDIF control circuit RBFIE RBFIF TBEIE TBEIF Figure 12.1.1 SPIA Configuration Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 12-1 (Rev. 1.2)

  • Page 120: Input/Output Pins And External Connections

    SDIn #SPISS0 SPICLKn #SPISS1 #SPISS #SPISS2 External SPI master device External SPI slave devices SPICLK SPICLK #SPISS SPICLK Figure 12.2.2.2 Connections between SPIA in Slave Mode and External SPI Master Device Seiko Epson Corporation 12-2 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 121: Pin Functions In Master Mode And Slave Mode

    16-bit timer channel and converts it to the SPICLKn. The 16-bit timer must be run with an appro- priate reload data set. The SPICLKn frequency (baud rate) and the 16-bit timer reload data are calculated by the equations shown below. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 12-3 (Rev. 1.2)

  • Page 122: Clock Supply In Debug Mode

    SDIn SDOn (Master mode) SDOn (Slave mode) SDOn (Slave mode) Writing data to the SPInTXD register Figure 12.3.3.1 SPI Clock Phase and Polarity (SPInMOD.LSBFST bit = 0, SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 12-4 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 123: Data Format

    1. Assert the slave select signal by controlling the general-purpose output port (if necessary). 2. Check to see if the SPInINTF.TBEIF bit is set to 1 (transmit buffer empty). 3. Write transmit data to the SPInTXD register. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 12-5 (Rev. 1.2)
  • Page 124 SPInTXD register Transmit data remained? Wait for an interrupt request (SPInINTF.TBEIF = 1) Negate the slave select signal output from a general-purpose port Figure 12.5.2.2 Data Transmission Flowchart in Master Mode Seiko Epson Corporation 12-6 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 125: Data Reception In Master Mode

    Software operations SPInRXD → Data (R) Data (W) → SPInTXD SPInRXD → Data (R) 1 (W) → SPInINTF.TENDIF Figure 12.5.3.1 Example of Data Receiving Operations in Master Mode (SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 12-7 (Rev. 1.2)

  • Page 126: Terminating Data Transfer In Master Mode

    SPInTXD register data written is completed. If no transmit data is written during this period, the data bits input from the SDIn pin are shifted and output from the SDOn pin without being modified. Seiko Epson Corporation 12-8 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 127 Data (W) → SPInTXD Data (W) → SPInTXD Software operations SPInRXD → Data (R) SPInRXD → Data (R) Figure 12.5.5.1 Example of Data Transfer Operations in Slave Mode (SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 12-9 (Rev. 1.2)

  • Page 128: Terminating Data Transfer In Slave Mode

    “Interrupt Controller” chapter. The SPInINTF register also contains the BSY bit that indicates the SPIA operating status. Figure 12.6.1 shows the SPInINTF.BSY and SPInINTF.TENDIF bit set timings. Seiko Epson Corporation 12-10 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 129: Control Registers

    Remarks SPInMOD 15–12 – – – 11–8 CHLN[3:0] 7–6 – – PUEN NOCLKDIV LSBFST CPHA CPOL Bits 15–12 Reserved Bits 11–8 CHLN[3:0] These bits set the bit length of transfer data. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 12-11 (Rev. 1.2)

  • Page 130: Spia Ch.n Control Register

    Note: The SPInMOD register settings can be altered only when the SPInCTL.MODEN bit = 0. SPIA Ch.n Control Register Register name Bit name Initial Reset Remarks SPInCTL 15–8 – 0x00 – – 7–2 – 0x00 – SFTRST MODEN Bits 15–2 Reserved Seiko Epson Corporation 12-12 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 131: Spia Ch.n Transmit Data Register

    0x00 – – 6–4 – – OEIF H0/S0 Cleared by writing 1. TENDIF H0/S0 RBFIF H0/S0 Cleared by reading the SPInRXD register. TBEIF H0/S0 Cleared by writing to the SPInTXD register. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 12-13 (Rev. 1.2)

  • Page 132: Spia Ch.n Interrupt Enable Register

    The following shows the correspondence between the bit and interrupt: SPInINTE.OEIE bit: Overrun error interrupt SPInINTE.TENDIE bit: End-of-transmission interrupt SPInINTE.RBFIE bit: Receive buffer full interrupt SPInINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation 12-14 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 133: C (I2C)

    OADR10 OADR[9:0] Slave mode GCEN controller SDALOW SCLLOW TXNACK TXSTART Master mode TXSTOP controller SCLn CLKSRC[1:0] CLKDIV[1:0] Clock generator DBRUN Baud rate SCLO MODEN BRT[6:0] generator CLK_I2Cn Figure 13.1.1 I2C Configuration Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 13-1 (Rev. 1.2)

  • Page 134: Input/Output Pins And External Connections

    • The internal pull-up resistors for the I/O ports cannot be used for pulling up SDA and SCL. • When the I2C is set into master mode, no other master device can be connected to the I bus. Seiko Epson Corporation 13-2 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 135: Clock Settings

    13.3.3.1). Note: The I C bus transfer rate is limited to 100 kbit/s in standard mode or 400 kbit/s in fast mode. Do not set a transfer rate exceeding the limit. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 13-3 (Rev. 1.2)

  • Page 136: Operations

    - Set the I2CnCTL.MST bit to 0. (Set slave mode) - Set the I2CnCTL.SFTRST bit to 1. (Execute software reset) - Set the I2CnCTL.MODEN bit to 1. (Enable I2C Ch.n operations) Seiko Epson Corporation 13-4 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 137: Data Transmission In Master Mode

    I2CnINTF.NACKIF bit = 1 (NACK received), the I2C Ch.n generates a repeated START condition. When the repeated START condition has been generated, the I2CnINTF.STARTIF and I2CnINTF.TBEIF bits are both set to 1 same as when a START condition has been generated. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 13-5 (Rev. 1.2)
  • Page 138 Last data sent? Retry? Write 1 to the I2CnCTL.TXSTOP bit Write data to the I2CnTXD register Wait for an interrupt request (I2CnINTF.STOPIF = 1) Figure 13.4.2.2 Master Mode Data Transmission Flowchart Seiko Epson Corporation 13-6 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 139: Data Reception In Master Mode

    This reading triggers the I2C Ch.n to start subsequent data reception. Generating a STOP or repeated START condition It is the same as the data transmission in master mode. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 13-7 (Rev. 1.2)
  • Page 140 Read receive data from the I2CnRXD register Write 1 to the I2CnCTL.TXSTOP bit Write 1 to the I2CnCTL.TXSTOP bit Wait for an interrupt request (I2CnINTF.STOPIF = 1) Figure 13.4.3.2 Master Mode Data Reception Flowchart Seiko Epson Corporation 13-8 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 141: 10-Bit Addressing In Master Mode

    Clear the I2CnINTF.STARTIF bit by writing 1 after the interrupt has occurred. 9. Write the first address to the I2CnTXD.TXD[7:1] bits and 1 that represents READ as the data transfer direc- tion to the I2CnTXD.TXD0 bit. 10. Perform data reception. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 13-9 (Rev. 1.2)

  • Page 142: Data Transmission In Slave Mode

    Go to Step 6 when a STOP condition interrupt has occurred. ii. Go to Step 2 when a START condition interrupt has occurred. 6. Clear the I2CnINTF.STOPIF bit and then terminate data sending operations. Seiko Epson Corporation 13-10 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 143 A: ACK, A: NACK, Saddr/R: Slave address + R(1), Saddr/W: Slave address + W(0), STARTIF = 1 Data n: 8-bit data Figure 13.4.5.1 Example of Data Sending Operations in Slave Mode Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 13-11 (Rev. 1.2)

  • Page 144: Data Reception In Slave Mode

    I2C Ch.n sends an ACK and pulls down SCL to low. The received data in the shift register is transferred to the receive data buffer and the I2CnINTF.RBFIF and I2CnINTF.BYTEENDIF bits are both set to 1. Af- ter that, the received data can be read out from the I2CnRXD register. Seiko Epson Corporation 13-12 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 145 Wait for an interrupt request (I2CnINTF.RBFIF = 1) Last data received next? Write 1 to the I2CnCTL.TXNACK bit Read receive data from the I2CnRXD register Last data received? Figure 13.4.6.2 Slave Mode Data Reception Flowchart Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 13-13 (Rev. 1.2)

  • Page 146: Slave Operations In 10-Bit Address Mode

    If SDA does not change from low when the I2C Ch.n outputs the ninth clock, it is regarded as an automatic bus clearing failure. In this case, the I2C Ch.n clears the I2CnCTL.TXSTART bit to 0 and sets both the I2CnINTF.ERRIF and I2CnINTF.STARTIF bits to 1. Seiko Epson Corporation 13-14 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 147: Error Detection

    4 <Master mode only> When 1 is written to the I2CnCTL.TX- I2CnINTF.ERRIF = 1 START bit while the I2CnINTF.BSY bit = 0 (Refer to “Automatic Automatic bus clearing I2CnCTL.TXSTART = 0 Bus Clearing Operation.”) failure I2CnINTF.STARTIF = 1 Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 13-15 (Rev. 1.2)

  • Page 148: Interrupts

    Master mode BRT + 3 CLK_I2Cn TXSTART = 1 TXSTART = 0 STARTIF = 1 Slave mode Address matching the I2CnOADR register BSY = 1 TR = 0/1 STARTIF = 1 Seiko Epson Corporation 13-16 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 149: Control Registers

    (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Note: The I2CnCLK register settings can be altered only when the I2CnCTL.MODEN bit = 0. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 13-17 (Rev. 1.2)

  • Page 150: I2C Ch.n Mode Register

    The I2CnOADR.OADR[9:0] bits are effective in 10-bit address mode (I2CnMOD.OADR10 bit = 1), or the I2CnOADR.OADR[6:0] bits are effective in 7-bit address mode (I2CnMOD.OADR10 bit = 0). Note: The I2CnOADR register settings can be altered only when the I2CnCTL.MODEN bit = 0. Seiko Epson Corporation 13-18 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 151: I2C Ch.n Control Register

    Bit 0 MODEN This bit enables the I2C operations. 1 (R/W): Enable I2C operations (The operating clock is supplied.) 0 (R/W): Disable I2C operations (The operating clock is stopped.) Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 13-19 (Rev. 1.2)

  • Page 152: I2C Ch.n Transmit Data Register

    0 (R): SDA = High level Bit 11 SCLLOW This bit indicates that SCL is set to low level. 1 (R): SCL = Low level 0 (R): SCL = High level Seiko Epson Corporation 13-20 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 153: I2C Ch.n Interrupt Enable Register

    Transmit buffer empty interrupt I2C Ch.n Interrupt Enable Register Register name Bit name Initial Reset Remarks I2CnINTE 15–8 – 0x00 – – BYTEENDIE GCIE NACKIE STOPIE STARTIE ERRIE RBFIE TBEIE Bits 15–8 Reserved Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 13-21 (Rev. 1.2)
  • Page 154 I2CnINTE.NACKIE bit: NACK reception interrupt I2CnINTE.STOPIE bit: STOP condition interrupt I2CnINTE.STARTIE bit: START condition interrupt I2CnINTE.ERRIE bit: Error detection interrupt I2CnINTE.RBFIE bit: Receive buffer full interrupt I2CnINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation 13-22 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 155: Lcd Driver (Lcd8A)

    Drive DSPREV control circuit SEGREV DSPAR Display data RAM COMREV DSPC[1:0] COMxDEN LCD power supply circuit LCD voltage LC[3:0] booster BSTEN HVLD VCSEL LCD voltage VCEN regulator Figure 14.1.1 LCD8A Configuration Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 14-1 (Rev. 1.2)

  • Page 156: Output Pins And External Connections

    2. Set the following LCD8CLK register bits: - LCD8CLK.CLKSRC[1:0] bits (Clock source selection) - LCD8CLK.CLKDIV[2:0] bits (Clock division ratio selection = Clock frequency setting) The CLK_LCD8A frequency should be set to around 32 kHz. Seiko Epson Corporation 14-2 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 157: Clock Supply In Sleep Mode

    V can be generated by the internal LCD power supply circuit (LCD voltage regu- lator and LCD voltage booster). One or all voltages can also be applied from outside the IC. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 14-3 (Rev. 1.2)

  • Page 158: Internal Generation Mode

    V . Set the LCD8PWR.VCSEL bit as shown in Table 14.4.4.1. Current consumption can be reduced by selecting reference voltage V as compared with reference voltage V Seiko Epson Corporation 14-4 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 159: Lcd Voltage Booster Setting

    7. Write display data to the display data RAM. 8. Set the following bits when using the interrupt: - Write 1 to the LCD8INTF.FRMIF bit. (Clear interrupt flag) - Set the LCD8INTE.FRMIE bit to 1. (Enable LCD8A interrupt) Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 14-5 (Rev. 1.2)

  • Page 160: Display On/Off

    COM0 to COM3 SEG0 to SEG31 128 segments COM0 to COM2 SEG0 to SEG31 96 segments COM0 to COM1 SEG0 to SEG31 64 segments Static COM0 SEG0 to SEG31 32 segments Seiko Epson Corporation 14-6 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 161: Drive Waveforms

    Figures 14.5.5.1 to 14.5.5.3 show some drive waveform examples. 1 frame LFRO display status COM0 COM0 COM1 COM2 COM3 COM1 COM4 COM5 COM6 COM7 COM2 SEGx COM3 COM4 COM5 COM6 COM7 SEGx Figure 14.5.5.1 1/8 Duty Drive Waveform Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 14-7 (Rev. 1.2)
  • Page 162 COM0 COM0 COM1 COM2 COM3 COM1 SEGx COM2 COM3 SEGx Figure 14.5.5.2 1/4 Duty Drive Waveform 1 frame LFRO display status COM0 COM0 SEGx SEGx Figure 14.5.5.3 Static Drive Waveform Seiko Epson Corporation 14-8 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 163: Partial Common Output Drive

    When 1/4 to 1/2 duty or static drive is selected, two screen areas can be allocated in the display data RAM, and the LCD8DSP.DSPAR bit can be used to switch between the screens. Setting the LCD8DSP.DSPAR bit to 0 selects display area 0; setting to 1 selects display area 1. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 14-9 (Rev. 1.2)

  • Page 164: Segment Pin Assignment

    – – – – – LCD8DSP.SEGREV · · · · · bit = 1 LCD8DSP.SEGREV · · · · · bit = 0 Figure 14.6.3.2 Display Data RAM Map (1/5 duty) Seiko Epson Corporation 14-10 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 165: Interrupt

    For more information on interrupt control, refer to the “Interrupt Controller” chapter. 1 frame LFRO COM0 COMx Figure 14.7.1 Frame Interrupt Timings (1/x duty) Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 14-11 (Rev. 1.2)

  • Page 166: Control Registers

    Note: If the LCD8CTL.MODEN bit is altered from 1 to 0 while the LCD panel is displaying, the LCD display is automatically turned off and the LCD8DSP.DSPC[1:0] bits are also set to 0x0. Seiko Epson Corporation 14-12 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 167: Lcd8A Timing Control Register

    – HVLD VCSEL VCEN Bits 15–12 LC[3:0] These bits set the LCD panel contrast. Table 14.8.3 LCD Contrast Adjustment LCD8PWR.LC[3:0] bits Contrast High (dark) ↑ ↓ Low (light) Bits 11–9 Reserved Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 14-13 (Rev. 1.2)

  • Page 168: Lcd8A Display Control Register

    Bit 11 COM3DEN Bit 10 COM2DEN Bit 9 COM1DEN Bit 8 COM0DEN These bits configure the partial drive of the common output pins. 1 (R/W): Normal output 0 (R/W): Off waveform output Seiko Epson Corporation 14-14 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 169: Lcd8A Interrupt Flag Register

    Bit 0 FRMIF This bit indicates the frame interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 14-15 (Rev. 1.2)

  • Page 170: Lcd8A Interrupt Enable Register

    LCD8INTE 15–8 – 0x00 – – 7–1 – 0x00 – FRMIE Bits 15–1 Reserved Bit 0 FRMIE This bit enables the frame interrupt. 1 (R/W): Enable interrupt 0 (R/W): Disable interrupt Seiko Epson Corporation 14-16 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 171: F Converter (Rfc)

    Time base counter DBRUN TC[23:0] MODEN Counter RFCLKOn control circuit Measurement counter MC[23:0] CONEN SSENB RFINn EVTEN CR oscillation SSENA Oscillation REFn SMODE[1:0] control circuit SREF circuit SENAn SENBn Figure 15.1.1 RFC Configuration Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 15-1 (Rev. 1.2)

  • Page 172: Input/Output Pins And External Connections

    Figure 15.2.2.1 Connection Example in Resistive Sensor DC Oscillation Mode SENBn SEN1 SENAn REFn RFINn : Reference resistor : Resistive sensor (AC bias) SEN1 S1C17 RFC : Oscillation capacitor Figure 15.2.2.2 Connection Example in Resistive Sensor AC Oscillation Mode Seiko Epson Corporation 15-2 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 173: Clock Settings

    (Clear interrupt flags) - Set the interrupt enable bits in the RFCnINTE register to 1. (Enable interrupts) 3. Assign the RFC input/output function to the ports. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 15-3 (Rev. 1.2)

  • Page 174: Operating Modes

    To obtain the difference between the reference oscillation and sensor oscillation clock count values from the measurement counter simply, appropriate initial values must be set to the measurement counter before starting reference oscillation. Seiko Epson Corporation 15-4 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 175: Converting Operations And Control Procedure

    The measurement counter overflow sets the RFCnINTF.EREFIF bit to 1 indicating that the reference oscil- lation has been terminated normally. If the RFCnINTE.EREFIE bit = 1, a reference oscillation completion interrupt request occurs at this point. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 15-5 (Rev. 1.2)
  • Page 176 Performing reference oscillation and sensor oscillation with the same resistor and capacitor results n ≈ m. The difference between n and m is a conversion error. Table 15.4.4.1 lists the error factors. (n: measurement counter initial value, m: measurement counter value at the end of sensor oscillation) Seiko Epson Corporation 15-6 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 177: Cr Oscillation Frequency Monitoring Function

    For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 15-7 (Rev. 1.2)

  • Page 178: Control Registers

    This bit sets the RFCLKOn pin to output the divided-by-two oscillation clock. 1 (R/W): Divided-by-two clock output 0 (R/W): Oscillation clock output For more information, refer to “CR Oscillation Frequency Monitoring Function.” Seiko Epson Corporation 15-8 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 179: Rfc Ch.n Oscillation Trigger Register

    This bit controls CR oscillation for sensor A. This bit also indicates the CR oscillation status. 1 (W): Start oscillation 0 (W): Stop oscillation 1 (R): Being oscillated 0 (R): Stopped Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 15-9 (Rev. 1.2)

  • Page 180: Rfc Ch.n Measurement Counter Low And High Registers

    Note: The time base counter must be set from the low-order value (RFCnTCL.TC[15:0] bits) first when data is set using a 16-bit access instruction. The counter may not be set to the correct value if the high-order value (RFCnTCH.TC[23:16] bits) is written first. Seiko Epson Corporation 15-10 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 181: Rfc Ch.n Interrupt Flag Register

    RFCnINTE.OVTCIE bit: Time base counter overflow error interrupt RFCnINTE.OVMCIE bit: Measurement counter overflow error interrupt RFCnINTE.ESENBIE bit: Sensor B oscillation completion interrupt RFCnINTE.ESENAIE bit: Sensor A oscillation completion interrupt RFCnINTE.EREFIE bit: Reference oscillation completion interrupt Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 15-11 (Rev. 1.2)

  • Page 182: Mr Sensor Controller (Amrc)

    DIF0IF DIRSET SENS_VAL RSKIPIF Unit counter PHASE[2:0] STPIF UCNT[11:0] REVRIF Comparator Ch.1 change Rotation detection NMLRIF Comparator Ch.0 change circuit Phase dropout Stop Reverse rotation Normal rotation Figure 16.1.1 AMRC Configuration Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 16-1 (Rev. 1.2)

  • Page 183: Input/Output Pins And External Connections

    EXHYS0 CMPIN0P CMPIN0N EXHYS1 CMPIN1P CMPIN1N SENSEN S1C17 AMRC One of various kind of analog output MR sensors Figure 16.2.2.2 Connections with an MR Sensor when External Hysteresis Resistors are Used Seiko Epson Corporation 16-2 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 184: Clock Settings

    - Write 1 to the interrupt flags in the AMRCINTF register. (Clear interrupt flags) - Set the interrupt enable bits in the AMRCINTE register to 1. (Enable interrupts) 8. Write 1 to the AMRCCTL.MODEN bit. (Enable AMRC operation) Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 16-3 (Rev. 1.2)

  • Page 185: Measurement Control And Operations

    The AMRC compares the sensor outputs between (+A) and (-A) and between (+B) and (-B) using the inter- nal comparators to detect a rotation angle in 45° units as shown in Table 16.4.2.1. Seiko Epson Corporation 16-4 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 186 When an underflow occurs in the counter, the AMRC presets the initial value to the counter again and sets the AMRCINTF.CNTxIF bit to 1. At the same time, an event counter Ch.x underflow interrupt request oc- curs if the AMRCINTE.CNTxIE bit = 1. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 16-5 (Rev. 1.2)

  • Page 187: Pulse Output Function

    For example, when f = 32,768 Hz, the pulse width can be set within the range from 15.6 ms (AMRCEVPLS. OSC1 EVW[5:0] bits = 0) to 1,000 ms (AMRCEVPLS.EVW[5:0] bits = 63). Seiko Epson Corporation 16-6 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 188: Hysteresis Control Function

    For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 16-7 (Rev. 1.2)

  • Page 189: Control Registers

    AMRCACTL.EXHYS1INV bit: External hysteresis 1 (CMPIN1P pin) AMRCACTL.EXHYS0INV bit: External hysteresis 0 (CMPIN0P pin) Bit 1 HYS1EN Bit 0 HYS0EN These bits enable the internal hysteresis. 1 (R/W): Enable internal hysteresis 0 (R/W): Disable internal hysteresis Seiko Epson Corporation 16-8 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 190: Amrc Pulse Control Register

    CTLST – – RSTUPCNT REVSTPTRG EPOUTTRG 3–0 TRGCYC[3:0] Bit 15 DIRSET This bit specifies the normal direction of rotation. 1 (R/W): Normal rotation = counterclockwise 0 (R/W): Normal rotation = clockwise Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 16-9 (Rev. 1.2)
  • Page 191 1 (R): Resetting 0 (R): Reset finished/in normal operations Bit 5 REVSTPTRG This bit selects the count source for the reverse/stop counter. 1 (R/W): Reverse rotation detected 0 (R/W): Stop detected Seiko Epson Corporation 16-10 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 192: Amrc Normal Rotation Counter Register

    The correct value may not be read during counting. The AMRCECNTx.ECNT[7:0] bits must be read twice and assume the counter value was read successfully if the two read results are the same. For more information on the event counter, refer to “Measurement Control and Operations.” Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 16-11 (Rev. 1.2)

  • Page 193: Amrc Unit Counter Compare Setting Register

    This bit indicates the comparator Ch.1 output status. 1 (R): 1 output 0 (R): 0 output Bit 10 FSENA This bit indicates the comparator Ch.0 output status. 1 (R): 1 output 0 (R): 0 output Bits 9–6 Reserved Seiko Epson Corporation 16-12 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 194: Amrc Interrupt Flag Register

    1 (W): Clear flag 0 (W): Ineffective The following shows the correspondence between the bit and interrupt: AMRCINTF.UCNTIF bit: Unit counter compare match interrupt AMRCINTF.CNT2IF bit: Event counter Ch.2 underflow interrupt Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 16-13 (Rev. 1.2)

  • Page 195: Amrc Interrupt Enable Register

    AMRCINTE.DIF1IE bit: Comparator Ch.1 change interrupt AMRCINTE.DIF0IE bit: Comparator Ch.0 change interrupt AMRCINTE.RSKIPIE bit: Phase dropout interrupt AMRCINTE.STPIE bit: Stop interrupt AMRCINTE.REVRIE bit: Reverse rotation interrupt AMRCINTE.NMLRIE bit: Normal rotation interrupt Seiko Epson Corporation 16-14 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 196: Electrical Characteristics

    *3 The component values should be determined after performing matching evaluation of the resonator mounted on the printed cir- cuit board actually used. *4 C is not required when the power-on-reset function is not used. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 17-1 (Rev. 1.2)

  • Page 197: Current Consumption

    µA RUN21 *1 OSC1 oscillator: CLGOSC1.INV1N[1:0] bits = 0x0, CLGOSC1.CGI1[2:0] bits = 0x0, CLGOSC1.OSDEN bit = 0, = 0 pF, Crystal resonator = C-002RX (manufactured by EPSON TOYOCOM Corporation, R = 50 kW (Max.), C = 7 pF) *2 The current consumption values were measured when a test program consisting of 60.5 % ALU instructions, 17 % branch instruc- tions, 12 % RAM read instructions, and 10.5 % RAM write instructions was executed continuously in the Flash memory.

  • Page 198: Clock Generator (Clg) Characteristics

    = 0 V, Ta = -40 to 85 °C Item Symbol Condition Min. Typ. Max. Unit Oscillation start time – – µs Oscillation frequency 25 °C 7.23 7.37 7.52 IOSC -40 to 85 °C 7.00 7.37 7.74 Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 17-3 (Rev. 1.2)

  • Page 199: Flash Memory Characteristics

    CLGOSC1.OSDEN bit = 1 – 0.025 µA OSD1 *1 Crystal resonator = C-002RX (manufactured by EPSON TOYOCOM Corporation, R = 50 kW (Max.), C = 7 pF) EXOSC external clock input characteristics Unless otherwise specified: V = 1.8 to 5.5 V, V = 0 V, Ta = -40 to 85 °C...

  • Page 200: Input/Output Port (Pport) Characteristics

    Ta = 85 °C, Min. value –V = 5.5 V = 3.6 V = 1.8 V = 1.8 V = 5.5 V = 3.6 V 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 17-5 (Rev. 1.2)

  • Page 201: Supply Voltage Detector (Svd) Characteristics

    *1 If CLK_SVD is configured in the neighborhood of 32 kHz, the SVDINTF.SVDDT bit is masked during the t period and it re- SVDEN tains the previous value. CLK_SVD SVDCTL.MODEN 0x1f 0x10 SVDCTL.SVDSC[1:0] SVDINTF.SVDDT Invalid Valid Invalid Valid SVDEN Seiko Epson Corporation 17-6 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 202: Uart (Uart) Characteristics

    = Pin load Common to master and slave modes SCYC SCKH SCKL SPICLKn (CPOL, CPHA) = (1, 0) or (0, 1) SPICLKn (CPOL, CPHA) = (1, 1) or (0, 0) SDIn SDOn Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 17-7 (Rev. 1.2)

  • Page 203: I 2 C (I2C) Characteristics

    * After this period, the first clock pulse is generated. SU:DAT SDAn HD:DAT SU:STA SU:STO HIGH HD:STA SCLn HD:STA S: START condition Sr: Repeated START condition 1st clock cycle 9th clock cycle P: STOP condition Seiko Epson Corporation 17-8 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 204: Lcd Driver (Lcd8A) Characteristics

    *1 Other LCD driver settings: LCD8PWR.LC[3:0] bits = 0xf, CLK_LCD8A = 32 kHz, LCD8TIM.FRMCNT[3:0] bits = 0x3 (frame fre- quency = 64 Hz) *2 The value is added to the current consumption in HALT/RUN mode. Current consumption increases according to the display contents and panel load. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 17-9 (Rev. 1.2)
  • Page 205 LCD circuit current-load characteristic Ta = 25 °C, Typ. value, LCD8PWR.LC[3:0] bits = 0xf, when a load is connected to the V pin only LCD8PWR.VCSEL bit = 0 LCD8PWR.VCSEL bit = 1 [µA] Seiko Epson Corporation 17-10 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 206: R/F Converter (Rfc) Characteristics

    1,000.0 1,000.0 100.0 100.0 ∆f /∆IC ∆f /∆IC RFCLK RFCLK 10.0 10.0 = 5.5 V = 5.5 V = 1.8 V = 1.8 V 1,000 10,000 1,000 10,000 100,000 [kΩ] [pF] Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 17-11 (Rev. 1.2)

  • Page 207: Mr Sensor Controller (Amrc) Characteristics

    MR sensor current, I and I HALT2 LCD2 currents included Measurement trigger cycle SENSEN SENSEN (CMPINnP) CMPINnN Comparator input ICCMP CMPINnP Comparator output (Internal analog signal) Comparator output latch signal Invalid (Internal digital signal) Seiko Epson Corporation 17-12 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 208: Basic External Connection Diagram

    Name Recommended components X'tal1 32 kHz crystal resonator C-002RX (R = 50 kW (Max.), C = 7 pF) manufactured by EPSON TOYOCOM Corporation OSC1 gate capacitor Trimmer capacitor or ceramic capacitor OSC1 drain capacitor Ceramic capacitor Bypass capacitor between V –V...

  • Page 209: Package

    19 PACKAGE 19 Package QFP13-64PIN (P-LQFP064-1010-0.50) (Unit: mm) INDEX 0.17–0.27 0.09–0.2 0ϒ –10ϒ 0.3–0.75 Figure 19.1 TQFP13-64PIN Package Dimensions Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL 19-1 (Rev. 1.2)

  • Page 210: Appendix A List Of Peripheral Circuit Control Registers

    5–4 CLKDIV[1:0] R/WP 3–2 – – 1–0 CLKSRC[1:0] R/WP 0x4042 CLGOSC 15–12 – – – (CLG Oscillation EXOSCSLPC Control Register) – – OSC1SLPC IOSCSLPC 7–4 – – EXOSCEN – – OSC1EN IOSCEN Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL AP-A-1 (Rev. 1.2)
  • Page 211 (ILVCLG) 0x4084 ITCLV2 15–11 – 0x00 – – (ITC Interrupt Level 10–8 ILV5[2:0] UART interrupt (ILVUART_0) Setup Register 2) 7–3 – 0x00 – – 2–0 ILV4[2:0] 16-bit timer Ch.0 interrupt (ILVT16_0) Seiko Epson Corporation AP-A-2 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 212 5–4 CLKDIV[1:0] R/WP 3–2 – – 1–0 CLKSRC[1:0] R/WP 0x40a2 WDTCTL 15–8 – 0x00 – – (WDT Control 7–5 – – Register) WDTCNTRST Always read as 0. 3–0 WDTRUN[3:0] R/WP – Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL AP-A-3 (Rev. 1.2)
  • Page 213 RTCAP Register) 13–12 RTCHH[1:0] 11–8 RTCHL[3:0] – – 6–4 RTCMIH[2:0] 3–0 RTCMIL[3:0] 0x40cc RTCMON 15–13 – – – (RTC Month/Day RTCMOH Register) 11–8 RTCMOL[3:0] 7–6 – – 5–4 RTCDH[1:0] 3–0 RTCDL[3:0] Seiko Epson Corporation AP-A-4 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 214 (SVD Status and In- SVDDT – terrupt Flag Register) 7–1 – 0x00 – SVDIF Cleared by writing 1. 0x4106 SVDINTE 15–8 – 0x00 – – (SVD Interrupt Enable 7–1 – 0x00 – Register) SVDIE Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL AP-A-5 (Rev. 1.2)
  • Page 215 Flag Register) 0x4208 P0INTCTL 15–8 P0EDGE[7:0] 0x00 – (P0 Port Interrupt 7–0 P0IE[7:0] 0x00 Control Register) 0x420a P0CHATEN 15–8 – 0x00 – – (P0 Port Chattering Filter Enable 7–0 P0CHATEN[7:0] 0x00 Register) Seiko Epson Corporation AP-A-6 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 216 (P2 Port Mode Select 7–0 P2SEL[7:0] 0x00 Register) 0x422e P2FNCSEL 15–14 P27MUX[1:0] – (P2 Port Function 13–12 P26MUX[1:0] Select Register) 11–10 P25MUX[1:0] 9–8 P24MUX[1:0] 7–6 P23MUX[1:0] 5–4 P22MUX[1:0] 3–2 P21MUX[1:0] 1–0 P20MUX[1:0] Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL AP-A-7 (Rev. 1.2)
  • Page 217 15–8 – 0x00 – – (P5 Port Chattering 7–6 P5CHATEN[7:6] Filter Enable Register) 5–0 – 0x00 – 0x425c P5MODSEL 15–8 – 0x00 – – (P5 Port Mode Select 7–0 P5SEL[7:0] 0x00 Register) Seiko Epson Corporation AP-A-8 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 218: 0X4380-0X438E Uart (Uart)

    Address Register name Bit name Initial Reset Remarks 0x4380 UA0CLK 15–9 – 0x00 – – (UART Ch.0 Clock DBRUN Control Register) 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL AP-A-9 (Rev. 1.2)
  • Page 219 – – (T16 Ch.1 Clock DBRUN Control Register) 7–4 CLKDIV[3:0] 3–2 – – 1–0 CLKSRC[1:0] 0x43a2 T16_1MOD 15–8 – 0x00 – – (T16 Ch.1 Mode 7–1 – 0x00 – Register) TRMD Seiko Epson Corporation AP-A-10 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 220 Cleared by reading the SPI0RXD register. TBEIF H0/S0 Cleared by writing to the SPI0TXD register. 0x43ba SPI0INTE 15–8 – 0x00 – – (SPIA Ch.0 Interrupt 7–4 – – Enable Register) OEIE TENDIE RBFIE TBEIE Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL AP-A-11 (Rev. 1.2)

  • Page 221: 0X43C0-0X43D2 I

    I2C0RXD register. TBEIF H0/S0 Cleared by writing to the I2C0TXD register. 0x43d2 I2C0INTE 15–8 – 0x00 – – (I2C Ch.0 Interrupt BYTEENDIE Enable Register) GCIE NACKIE STOPIE STARTIE ERRIE RBFIE TBEIE Seiko Epson Corporation AP-A-12 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 222 (T16 Ch.3 Interrupt 7–1 – 0x00 – Flag Register) UFIF Cleared by writing 1. 0x512c T16_3INTE 15–8 – 0x00 – – (T16 Ch.3 Interrupt 7–1 – 0x00 – Enable Register) UFIE Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL AP-A-13 (Rev. 1.2)
  • Page 223 (SPIA Ch.1 Control 7–2 – 0x00 – Register) SFTRST MODEN 0x5274 SPI1TXD 15–0 TXD[15:0] 0x0000 – (SPIA Ch.1 Transmit Data Register) 0x5276 SPI1RXD 15–0 RXD[15:0] 0x0000 – (SPIA Ch.1 Receive Data Register) Seiko Epson Corporation AP-A-14 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)
  • Page 224 7–3 – 0x00 – HVLD VCSEL VCEN 0x5408 LCD8DSP COM7DEN – (LCD8A Display COM6DEN Control Register) COM5DEN COM4DEN COM3DEN COM2DEN COM1DEN COM0DEN – – SEGREV COMREV DSPREV – – DSPAR 1–0 DSPC[1:0] Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL AP-A-15 (Rev. 1.2)
  • Page 225 Flag Register) OVTCIF Cleared by writing 1. OVMCIF ESENBIF ESENAIF EREFIF 0x5450 RFC0INTE 15–8 – 0x00 – – (RFC Ch.0 Interrupt 7–5 – – Enable Register) OVTCIE OVMCIE ESENBIE ESENAIE EREFIE Seiko Epson Corporation AP-A-16 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 226: 0X5480-0X549E Mr Sensor Controller (Amrc)

    0x000 Register) 0x5494 AMRCUCNT 15–12 – – – (AMRC Unit Counter 11–0 UCNT[11:0] 0x000 Cleared by writing 1 to the Register) AMRCCTL.RSTUPCNT bit or writing data to the AMR- CUCMP.UCMP[11:0] bits. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL AP-A-17 (Rev. 1.2)

  • Page 227: 0Xffff90

    RSKIPIE – STPIE REVRIE NMLRIE 0xffff90 Debugger (DBG) Address Register name Bit name Initial Reset Remarks 0xffff90 DBRAM 31–24 – 0x00 – – (Debug RAM Base 23–0 DBRAM[23:0] 0x00 Register) 0fc0 Seiko Epson Corporation AP-A-18 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 228: Appendix B Power Saving

    • Using a crystal resonator with lower C value decreases current consumption. However, these configurations may reduce the oscillation margin and increase the frequency error, therefore, be sure to perform matching evaluation using the actual printed circuit board. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL AP-B-1 (Rev. 1.2)

  • Page 229: Other Power Saving Methods

    • Setting the LCD voltage regulator into heavy load protection mode (LCD8PWR.HVLD bit = 1) increases current consumption. Heavy load protection mode should be set only when the display becomes unstable. Seiko Epson Corporation AP-B-2 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 230: Appendix C Mounting Precautions

    Sudden power supply fluctuations due to noise will cause malfunctions. Consider the following issues. (1) Connections from the power supply to the V and V pins should be implemented via the shortest, thick- est patterns possible. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL AP-C-1 (Rev. 1.2)
  • Page 231 (2) Electromagnetically-induced noise from a solder iron when soldering In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po- tential as the IC GND. Seiko Epson Corporation AP-C-2 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 232: Appendix D Measures Against Noise

    • Execute the resending process via software after executing the receive error handler with a parity check. For details of the pin functions and the function switch control, see the “I/O Ports” chapter. For the UART con- trol and details of receive errors, see the “UART” chapter. Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL AP-D-1 (Rev. 1.2)

  • Page 233: Appendix E Initialization Routine

    ; Flash read wait cycle Xld.a %r0, 0x00 ; 0x00 = No wait or 0x01 = 1 wait ...(5) ld.b [%r1], %r0 ; [0x41b0] <= 0x00 ; ===== Main routine ========================================= Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL AP-E-1 (Rev. 1.2)
  • Page 234 “intXX_handler” can be used for software interrupts. (3) The program code is written in the “.text” section. (4) Sets the stack pointer. (5) Sets the number of Flash memory read cycles. (See the “Memory and Bus” chapter.) Seiko Epson Corporation AP-E-2 S1C17M01 TECHNICAL MANUAL (Rev. 1.2)

  • Page 235: Revision History

    REVISION HISTORY Revision History Code No. Page Contents 412361700 New establishment 412361700c 2-10 2.4.1 Initial Boot Sequence (Old) – (New) For the reset hold time t , refer to “Reset hold circuit characteristics” in the “Electrical Charac- RSTR teristics” chapter. 3.3.4 External Connection (Old) For the recommended pull-up resistor value, refer to “Recommended Operating Conditions, DSIO pull-up resistor R...
  • Page 236 REVISION HISTORY Code No. Page Contents 412361700c 13-12 13.4.6 Data Reception in Slave Mode (Old) Data receiving procedure 7. Repeat Steps 4 to 6 until the end of data reception. (New) Data receiving procedure 7. Repeat Steps 4 to 6 until the end of data reception. 8.
  • Page 237 REVISION HISTORY Code No. Page Contents 412361701 ITC: ITC Interrupt Request Processing (Old) Note: Wake-up operations (SLEEP/HALT cancellation) by an interrupt cannot be disabled even if the interrupt level is set to 0. (New) Deleted ITC: NMI (Old) The watchdog timer embedded in this IC can generate a non-maskable interrupt (NMI). This inter- rupt takes precedence over other interrupts and is unconditionally accepted by the CPU.
  • Page 238 REVISION HISTORY Code No. Page Contents 412361701 WDT: During SLEEP mode (Old) WDT operates in SLEEP mode if the selected clock source is running. In this case SLEEP mode is cleared by an NMI or reset if it continues for more than the NMI/reset generation cycle and the NMI or reset handler is executed.
  • Page 239 REVISION HISTORY Code No. Page Contents 412361701 10-1 T16: Figure 10.1.1 Configuration of a T16 Channel Modified the figure (The I/O port (chattering filter) was deleted.) T16: Input Pin (Old) If the port is shared with the EXCLm pin and other functions, the EXCLm input function must be assigned to the port before using the event counter function.
  • Page 240 REVISION HISTORY Code No. Page Contents 412361702 8.3.2 Theoretical Regulation Function Corrected Step 1. 1. Measure f and calculate the frequency tolerance correction value OSC1 “m [ppm] = -{(f - 32,768 [Hz]) / 32,768 [Hz]} × 10 .” OSC1 (Eq. 8.1) m: OSC1 frequency tolerance correction value [ppm] 8.4.2 Real-Time Clock Counter Operations Corrective operation when a value out of the effective range is set Added a note.
  • Page 241 REVISION HISTORY Code No. Page Contents 412361702 AP-A-9 Appendix A List of Peripheral Circuit Control Registers PDIOEN (Pd Port Enable Register) Modified the register table. PDOEN[1:0] → PDOEN[2:0]...
  • Page 242 Fax: +86-10-3299-0560 Epson Europe Electronics GmbH Riesstrasse 15, 80992 Munich, Germany Phone: +49-89-14005-0 Fax: +49-89-14005-110 Epson Taiwan Technology & Trading Ltd. 15F, No.100, Songren Rd, Sinyi Dist, Taipei City 110, Taiwan Phone: +886-2-8786-6688 Epson Singapore Pte., Ltd. 1 HarbourFront Place,...

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