Sharp BE-2520 Service Manual page 30

0.1nF =
m
from power 5V
supply circuit
iN D6
56KaQ = « 1588L1X2
>
~ ee ee | cae
12 =
0, 11
>
5-3. Signal description table
CPU, ROM; RAM
Description
Basic clock pulse
= L_
12
t1: 0.43 ~ 0.53us
t2: 0.86 ~ 1.05zis
Power off signal
Power on; High, Power off: Low
| Originated in power supply PWB. —
1/0 device request t/O designation: Low
(Key, Display; Printer etc.)
Power on state: High, Power off: Low
Halt CPU. halt state: Low
Interrupt input. for. printer controller
Write
Read
* Data bus
Address bus
" | Buzzer Low: Buzzer on
P-ROM1 select signal
Not used
~ RAM select signal
®@ FOR FURTHER DESCRIPTION OF THE CPU Z-80,
REFER TO THE "CASH REGISTER BASIC
MANUAL".
CPU LHO080/UPD780°
BE-2520
wf ink RESET
40H 000
- g yo b 1
soll 8)
Be)
Tall 8) 3
RESET
' * 930PI x 330PF
RES
RES
Fig. 3
Fig. 5
P-ROM 27128R091A: 16K bytes
RAM pPD449: 2K bytes
The CPU will address ROM or RAM
address bus lines.
Once
it has been established
(by the CPU) which
memory has been chip selected and addressed, reading or
writing will take place via the data bus lines (D0 ~ D7)
by a unit of eight bits.
a:
Read and write for the RAM are identified by the WR
(write) signal.
directly by 'the