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DEGQ-7200
@ Pin Functions (PD2038C)
0
go de@t eof PO... 20) 1 Test Cate
Outta
|
4 | VDD
||
Power supply terminal forlogic circuit
a
es RE
IO IC) <0 eae ee
a
eae
ore eee,
| 6-11 | TP5-0
| O | Test data output
|
|
Cae
|
| 12 | vvSSR_ |
| GND terminal forinternaldelayRAM
| 13 | DDR
| | ~Power supply terminal for internaldelayRAM
A
ea lee So
ND ee
re
oa
ee
ee
| 15-17, | SbdO20 | O | Serialdataoutput oo
p ABO 1h SDN O25)
Serial data inpert ( isy o
a
e
ce QUE ee OR eee. le esl UR clock input (is) soe a
ee ee
| 27 | WK
| OO | Wordclockoutput,
| 22]
FS32_—— | | Bitclockoutput(32fs)
| 23 | = FS64
| | CBitclockoutput(64fs)
| 24 | EBCO. CUT
| «CBitclockinput,
es ee
ERO
le We 2 UR COCO
no
a
es eh
|
| 28,29 | ELRIVO | 1 | LRclockinputt
|
30.—O| 6SYNC.
| ts
Synchronizing signal input
Power suoply terminal for logic circuit
vstal oscillating element connection pin or external clock inp
Crystal oscillating element connection pin
31
SSRs
nC
Oo
©
S| | -
O
_
System clock select input
stal oscillation mode or VCO oscillation mode select input
ata output from phase comparator
nalog GND
w pass filter amplifier output
ow pass filter amplifier input
|
nalog power supply
|
est terminal
O{iM1G)
z= O
o
As No
5 G2 109109
G21
W (OW
|G
+
m7
WY
2°
N
RST |
Reset signal input terminal
| cS
__-__—i|_i__'{
Chip select input
IFCD
| 1
|. Command or data select input from DSP controller
IFDI
| Lt | Data input from DSP controller
|
}
i 49 | IFDO
|. O- | DataoutputforDSP controller
|
IFCK
| |
| - Shift clock input from DSP controller
Acknowledge
signal output for DSP controller
GND
|
Test data output
|
NJM2100M
13
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