Siemens FUJITSU S383FA-V151 Service Manual
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Siemens FUJITSU S383FA-V151 Service Manual

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SERVICE MANUAL
S383FA-V151
P/N : 41A50-137

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Summary of Contents for Siemens FUJITSU S383FA-V151

  • Page 1 SERVICE MANUAL S383FA-V151 P/N : 41A50-137...
  • Page 2 THESE DOCUMENTS ARE FOR REPAIR SERVICE INFORMATION ONLY. EVERY REASONABLE EFFORT HAS BEEN MADE TO ENSURE THE ACCURACY OF THIS MANUAL; WE CANNOT GUARANTEE THE ACCURACY OF THIS INFORMATION AFTER THE DATE OF PUBLICATION AND DISCLAIMS RE LIABILITY FOR CHANGES, ERRORS OR OMISSIONS, MANUFACTURE DATA : NOVEMBER.

  • Page 3: Table Of Contents

    TABLE OF CONTENTS PAGE 1. SPECIFICATIONS ....................GENERAL SPECIFICATIONS ...........…....LCD MONITOR DESCRIPTION ..............INTERFACE CONNECTOR ..............……. 2. PRECAUTION AND NOTICES ................ASSEMBLY PRECAUTION ................. OPERATIONG PRECAUTION ..............STORAGE PRECAUTION …................ HIGH VOLTAGE WARNING ............... 3. OPERATING INSTRUCTIONS ................4. ADJUSTMENT ......................ADJUSTMENT CONDITIONS AND PRECAUTIONS .......

  • Page 4: Specifications

    1. SPECIFICATIONS FOR LCD MONITOR General specifications LCD-PANEL : Active display area 15 inches diagonal Pixel pitch 0.298 mm x 0.298 mm Pixel format 1024 x 768 RGB vertical stripe arrangement Display Color : 6-bit, 262144 colors External Controls : Power On/Off, Auto key, Rotary-knob, Contrast, Brightness, Focus, Clock, H-position, V-position, Language, Recall-7800, Recall-6500, Reset, Exit-osd, Red, Green, Blue...

  • Page 5: Lcd Monitor Description

    LCD MONITOR DESCRIPTION The LCD MONITOR will contain an main board, an inverter board, a power switch board and a keyboard. The main board will house the flat panel control logic, brightness control logic, DDC and DC-DC conversion to supply the appropriate power to the whole board and LCD panel, and transmitting TTL level signals into LCD Module to drive the LCD display circuit.

  • Page 6: Precaution And Notices

    2. PRECAUTIONS AND NOTICES ASSEMBLY PRECAUTION (1) Please do not press or scratch LCD panel surface with anything hard. And do not soil LCD panel surface by touching with bare hands (Polarizer film, surface of LCD panel is easy to be flawed) In the LCD panel, the gap between two glass plates is kept perfectly even to maintain display characteristic and reliability.

  • Page 7: Operating Instructions

    3. OPERATING INSTRUCTIONS This procedure gives you instructions for installing and using the LM500 LCD monitor display. Position the display on the desired operation and plug the power cord into a convenient AC outlet. Three- wire power cord must be shielded and is provided as a safety precaution as it connects the chassis and cabinet to the electrical conduct ground.

  • Page 8: Adjustment

    4. ADJUSTMENT ADJUSTMENT CONDITIONS AND PRECAUTIONS Approximately 30 minutes should be allowed for warm up before proceeding. Adjustments should be undertaken only on following function : contrast, brightness focus, clock, h-position, v-position, red, green, blue since 6500 color & 7800 color &VR501 have been carefully preset at the factory.

  • Page 9: Front Panel Control Knobs

    Clock adjustment Set the Chroma at pattern 63 (cross-talk pattern) or WIN98/95 shut-down mode (dot-pattern). Adjust until the vertical-shadow as wide as possible or no visible. This function is adjust the PLL divider of ADC to generate an accurate pixel clock Example : Hsyn = 31.5KHz Pixel freq.

  • Page 10: Circuit Description

    5. CIRCUIT-DESCRIPTION THE DIFFERENT between LG-Panel & Samsung-Panel & CPT-Panel & Hannstar- Panel in ELECTRICAL Charateristic LG-Panel 1. Two CCFL (Cold Cathode Fluorescent Tube) 2. Single Pixel, 6 bit color (262144 colors) 3. Panel Vdd = 3.3V (in JP202 select 3.3V) Samsung-Panel 1.

  • Page 11: Simple Introduction About Lm500 Chipset

    SIMPLE-INTRODUCTION about LM500 chipset GMZAN1 (Genesis all-in-one solution for ADC, OSD, scalar and interpolation) : USE for computer graphics images to convert analog RGB data to digital data for interpolation process, zooming, OSD font & overlay and generate drive-timing for LCD-PANEL, M6759 (ALI- MCU, type 8052 series with 64k Rom-size and 512 byte ram) : Use for calculate frequency, pixel-dot , detect change mode, rs232-communication, power-consumption control, OSD-index warning…etc.

  • Page 12: Trouble Shooting Chart

    6. Trouble-Shooting **Use the PC Win 98/95 white pattern, with some icon on it, and Change the Resolution to 640x480 60 Hz / 31 **NOTICE : This system free-running freq. is 48 KHz / 60 Hz, so you better use another frequency to do trouble shooting(ex:31kHz 60Hz) this trouble shooting is proceed with 640x480 @60Hz 31Khz NO SCREEN APPEAR OK, led in green-state...
  • Page 13 Check MCU reset circuit if normal ? Check MCU relative reset circuit U302 pin 10 = low to high when C313, R313, D301 !! Power-on?? Check GMZAN1 relative reset circuit Check R229 reset for GMZAN1= high to R326,C314,D302,R229 Low twice when power-on ?? NG, no transition Measured PCLK(pin 44 from CN201) Check input connector CN200 is loose??
  • Page 14 PERIPHERAL PANEL BLOCK Note: “Panel vdd “ and “backlight on-off ” can be direct control by : GMZAN1 or MCU Some panel can direct control by GMZAN1 ,if the relative timing between panel-vdd and backlight on-off is short ( under 80 ms) , otherwise, will be control by MCU If J211 be connected, that means Panel-VDD control was by GMZAN1 ,otherwise by MCU( JP212) If J300 be connected, that means Backlight control was by GMZAN1 ,otherwise by MCU ( JP301) BUT Hannstar panel &...
  • Page 15 GMZAN1 BLOCK check Note : set the input signal ( PC or CHROMA) to 640x480 31k 60 hz Check input connector CN200 is loose?? Tighten CN200 cable & check relative circuit Measure R212,R211= 31K & 60 hz ? Measure R200,R201,R202 (RGB input ) had signal?? Measure U201 oscillator 50MHz is normal?? Replace U201 oscillator 50 MHz...
  • Page 16 KEYBOARD BLOCK check Check U302 MCU pin 43,42,41,40,39 at Mechanical was stuck, Check ! High state(5V)? without press any key Replace Tact-switch SW105 at keyboard if still no work replace U302 MCU at main-board and Press power key and check U302 pin 43 check MCU relative reset circuit, and crystal = low (0V) ? Check U302 pin 38 (LED green) will have...
  • Page 17 POWER-BLOCK check *Note : the waving of U304 pin 2 can determined the power situation stable rectangle wave with equal duty, freq around 150K-158KHz that means all power of this interface board is in normal operation ,all status of 5V & 3.3V is normal working unstable rectangle wave without same duty, that means ABNORMAL operation was happened check 3.3V or 5V ,short-circuit or bad component rectangle wave with large spike &...
  • Page 18 II.ALL SCREEN HAS INTERFERENCES OR NOISE, CAN’T BE FIXED BY AUTO KEY ** NOTE: There is so many kind of interferences, 1). One is cause by some VGA-CARD that not meet VESA spec or power grounding too bad that influence our circuit 2).other is cause by external interferences, move the monitor far from electronic equipment.( rarely happened) Use DOT-pattern, or win98/99 shut-down...
  • Page 19 III. DOS MODE has jitter NOTE :the rule of doing AUTO-CONFIGURATION : must be a full-size screen, if the screen not full , the auto- configuration will fail. So in dos mode ,just set your “CLOCK” in OSD-MENU to zero or use some full screen edit file (ex: PE2, HE) and press “AUTO”...
  • Page 20 V. THE PANEL LUMINANCE WAS DOWN ± ±...
  • Page 21 GMZAN1 The gmZAN1device utilizes Genesis’ patented third-generation Advanced Image Magnification technology as well as a proven integrated ADC/PLL to provide excellent image quality within a cost effective SVGA/XGA LCD monitor solution. As a pin-compatible replacement for the gmB120, the gmZAN1 incorporates all of the gmB120 features plus many enhanced features;...
  • Page 22 1.3 Pin Description Unless otherwise stated, unused input pins must be tied to ground, and unused output pins left open. Table 1 : Analog-to-Digital Converter PIN # Name I/O Description Digital power for ADC encoding logic. Must be bypassed with 0.1uF capacitor to ADC_VDD2 pin 78 (ADC_GND2) Digital GND for ADC encoding logic.
  • Page 23 Table 2 : Host Interface (HIF) / External On-Screen Display PIN # Name I/O Description Host Frame Sync. Frames the packet on the serial channel. Clock signal input for the 3-wire serial communication. HCLK Data signal for the 3-wire serial communication. HDATA Resets the gmZAN1 chip to a known state when low.
  • Page 24 Table 3 : Clock Recovery / Time Base Conversion PIN # Name I/O Description Digital power for Destination DDS (direct digital synthesizer). Must be bypassed DVDD with a 0.1uF capacitor to digital ground plane. Analog ground for Destination DDS DAC. Must be directly connected to the DAC_DGNDA analog system ground plane.
  • Page 25 Table 4. TFT Panel Interface Description PIN # Name 2pxl/clk 2pxl/clk 1pxl/clk 1pxl/clk 8bit 6-bit 8-bit 6-bit PD47 PD46 PD45 PD44 PD43 PD42 PD41 PD40 PD39 PD38 PD37 PD36 PD35 PD34 PD33 PD32 PD31 PD30 PD29 PD28 PD27 PD26 PD25 PD24 PD23 PD22...
  • Page 26 Description PIN # Name 2pxl/clk 2pxl/clk 1pxl/clk 1pxl/clk 8bit 6-bit 8-bit 6-bit PdispE This output provides a panel display enable signal that is active when flat panel data is valid. This output provides the panel line clock signal. This output provides the frame start signal. PCLKA This output is used to drive the flat panel shift clock.
  • Page 27 1.4 System-level Block Diagram CVDD ADC_VDD RVDDA gmZAN1 Core ADC_GND RGNDA Blue TCLK Green SVDDA RVDDA Hsync To Clock SGNDA Vsync Generator DVDDA DGNDA R+,G+,B+ Even Data On-Screen OSD-FSW OSD-FSW PCLKA Display OSD-CLK Controller OSD-HREF OSD-VREF PDISPE Odd Data MPU with HCLK EPROM +12V...
  • Page 28 1.5 Operating Modes The Source Clock (also called SCLK in this document) and the Panel Clock are defined as follows: The Source Clock is the sample clock regenerated from the input Hsync timing (called clock recovery) by SCLK DDS (direct digital synthesis) and the PLL. The Panel Clock is the timing clock for panel data at the single pixel per clock rate.
  • Page 29 1.5.4 Downscaling Panel Clock frequency < Source Clock frequency Panel Hsync frequency < Input Hsync frequency Panel Vsync frequency = Input Vsync frequency This mode is used when the input resolution is greater than the panel resolution, to provide enough of a display to enable the user to recover to a supported resolution.
  • Page 30 2. FUNCTIONAL DESCRIPTION Figure 3 below shows the main functional blocks inside the gmZAN1 2.1 Overall Architecture Figure 3. Block Diagram for gmZAN1 On-Screen Display Control Analog Triple Source Scaling Gamma Panel Timing Engine Control Timing Panel Measurement (CLUT) Control / Generation Dither Pixel...
  • Page 31 The SCLK frequency (1/SCLK period) can be set to the range of 10-to-135 MHz. Using the DDS (direct digital synthesis) technology the clock recovery circuit can generate any SCLK clock frequency within this range. The pixel clock (DCLK or destination clock) is used to drive a panel when the panel clock is different from SCLK (or SCLK/2).
  • Page 32 The table below summarizes the characteristics of the clock recovery circuit. Table 7. Clock Recovery Characteristics Minimum Typical Maximum SCLK Frequency 10MHz 135 MHz Sampling Phase Adjustment 0.5 ns/step, 64 steps Patented digital clock synthesis technology makes the gmZAN1 clock circuits very immune to temperature/voltage drift.
  • Page 33 2.3 Analog-to-Digital Converter 2.3.1 Pin Connection The RGB signals are to be connected to the gmZAN1 chip as described in Table 8 and Table 9. Table 8. Pin Connection for RGB Input with Hsync/Vsync GmZAN1 Pin Name (Pin Number) CRT Signal Name Red+(#95) Red- (#94) N/A (Tie to Analog GND for Red on the board)
  • Page 34 2.3.2 Sync. Signal Support The gmZAN1 chip supports digital separate sync (Hsync/Vsync), digital composite sync, and analog composite sync (also known as sync-on-green). All sync types are supported without external sync separation / extraction circuits. Digital Composite Sync The types of digital composite sync inputs supported are: OR/AND type: No Csync pulses toggling during the vertical sync period XOR type: Csync polarity changes during the vertical sync period...
  • Page 35 The display start/end registers store the first and the last pixels/lines of the last frame that have RGB data above a programmed threshold. The reference point of the STM block is the same as that of the source timing generator (STG) block: The first pixel: the pixel whose SCLK rising edge sees the transition of the HSYNC polarity from low to high.
  • Page 36 2.5.1 Scaling Filter The gmZAN1 scaling filter uses an advanced adaptive scaling technique proprietary to Genesis Microchip Inc. and provides high quality scaling of real time video and graphics images. This is Genesis’ third generation scaling technology that benefits from the expertise and feedback gained by supporting a wide range of solutions and applications.
  • Page 37 Table 13. gmZAN1 TFT Panel Interface Timing Signal Name Typical Unit Period 16.67 2048 lines Frequency Front porch 2048 lines Back porch 2048 lines Pulse width 2048 lines PdispE Panel height 2048 lines Disp. Start from VS t6 2048 lines PVS set up tp PHS 2048 PCLK *1...
  • Page 38 Figure 7. timing Diagrams of the TFT Panel Interface (One pixel per clock) (a) Vertical size in TFT (b) Vsync width and display position in TFT RGBs (c) Horizontal size in TFT PCLK RGB data from data paths Panel Background Color Displayed (d) Hsync width in TFT...
  • Page 39 Figure 8. Data latch timing of the TFT Panel Interface (a) Two pixel per clock mode in TFT PCLK R2,(N:0) R4,(N:0) R0,(N:0) G0,(N:0) G2,(N:0) B2,(N:0) B0,(N:0) R1,(N:0) R3,(N:0) G1,(N:0) G3,(N:0) B1,(N:0) B3,(N:0) (b) One pixel per clock mode in TFT PCLK R(n:0) G(n:0)
  • Page 40 2.6.2.1 State 0 (Power Off) The Pbias signal and Ppower signal are low (inactive). The panel controls and data are forced low. This is the final state in the power down sequence. PM is kept in state 0 until the panel is enabled. 2.6.2.2 State 1 (Power On) Intermediate step 1.
  • Page 41 2.6.3 Panel Interface Drive Strength As mentioned previously, the gmZAN1 has programmable output pads for the TFT panel interface. Three groups of panel interface pads (panel clock, data, and control) are independently controllable and are programmed using API calls. See the API reference manual for details. Table 14.
  • Page 42 2.7.1 Serial Communication Protocol In the serial communication between the microcontroller and the gmZAN1, the microcontroller always acts as an initiator while the gmZAN1 is always the target. The following timing diagram describes the protocol of the serial channel of the gmZAN1 chip. Figure 10.
  • Page 43 Table 15 summarizes the serial channel specification of the gmZAN1. Refer to Figure 10 for the timing parameter definition. Table 15. gmZAN1 Serial Channel Specification Parameter Min. Typ. Max. Word Size (Instruction and Data) 12 bits HCLK low to HFS high (t1) 100 ns HFS low to HCLK inactive (t2) 100 ns...
  • Page 44 2.8.1 OSD Color Map Both the internal and external OSD display use a 16 location SRAM block for the color programming. Each color location is a twelve-bit value that defines the upper four bits of each of the 8 bit Red, Blue and Green color components as follows: D3:0 Blue;...
  • Page 45 To improve the appearance and make it easy to find the OSD window on the screen, the user may select optional shadowing (3D effect). The “Shadow” feature operates in the same manner as in the B120; that is, it produces a region of half intensity (scaler data) pixels of the same width and height as the OSD window, but offset to the right and down by 8 pixels/lines (the border width setting has no effect).
  • Page 46 3. ELECTRICAL CHARACTERISTICS Table 20. Absolute Ratings Parameter Min. Typ. Max. Note PVDD 5.6 volts CVDD 5.6 volts Vss-0.5 volt Vcc+0.5V Operating temperature 0 degree C 70 degree C Storage temperature -65 degree C 150 degree C Maximum power consumption Table 21.

  • Page 47: Mechanical Of Cabinet Front Dis-Assembly

    MECHANICAL OF CABINET FRONT DIS-ASSEMBLY SCREW Q1A340-16-128X4 REAR COVER 34A675 SHIELD 85A548 MAIN BOARD MAIN FRAME 15A5683(HANNSTAR) SCREW Q1A1030-12-128X4 INVERTER SHIELD 85A577 LCD PANEL 750ALCDX41-1 INVERTER BOARD 79AL15-6-S SUPPORT(BACK) 34A677 ADAPTER BOARD 80AL15-2-L1 HINGE SUPPORT(FRONT) 37A442 34E676 KEPC KEPC560EKMN SHIELD KEY PAD 85A580 33A4095...
  • Page 48 44A 3229- CARTON 44A 3231- 44A 3231- 44A 3231- EVA(DOUBLE) 113- PROTECT COVER 116- PROTECT COVER 120- PE-LD BAG L15- DRIVE DISK SIEMENS 100- CORD 548- SHIELD CBPC 557- SHIELD INVERTORY 562- EARTH CLIP 580- SHIELD INVERTORY 581- PANED SHILED...
  • Page 49 PARTS LIST OF CONVERSION BOARD LOCATION CBPC1560GHMN SPECIFICATION CN303 33A 3802- WAFER 5P PLUG RIGHT ANELE CN302 33A 3802- WAFER 9P PLUG RIGHT ANELE CN202 33A 3804- WAFER FH12-30S-0.5SH CN201 33A 3804- WAFER FH12-45S-0.5SH CN200 33A 8013- 14 - 13P PLUG RIGHT ANGLE 152- LABEL U200...
  • Page 50 LOCATION CBPC1560GHMN SPECIFICATION R209 61A 0603- CHIP 2K OHM 1/10W R210 61A 0603- CHIP 2K OHM 1/10W R226 61A 0603- CHIP 3K OHM 1/10W R229 61A 0603- CHIP 510 OHM 1/10W R204 61A 0603- CHIP 75 OHM 1/10W R205 61A 0603- CHIP 75 OHM 1/10W R206 61A 0603-...
  • Page 51 LOCATION CBPC1560GHMN SPECIFICATION C311 65A 0603- 104 - CHIP 0.1UF 10V C250 65A 0603- 330 - 33PF 50V NPO C262 65A 0603- 330 - 33PF 50V NPO C303 65A 0603- 330 - 33PF 50V NPO C306 65A 0603- 330 - 33PF 50V NPO C307 305-...
  • Page 52 PARTS LIST OF KEY PC BOARD LOCATION KEPC560EKMN SPECIFICATION 152- KEPC560EEKMN-A LABEL Q101 419- PP - TR. 2PC945P Q102 419- PP - TR. 2PC945P R101 602- 103 - 10K OHM +-5% 1/6W R102 602- 103 - 10K OHM +-5% 1/6W R103 602- 103 -...

  • Page 53: Power System And Consumption Current

    POWER SYSTEM AND CONSUMPTION CURRENT ADAPTER MODULE INVERTER MODULE Input AC 110V, 60Hz/240V, 50Hz Input DC 12V Output DC 12V 3.5A Output AC 1500V/30K-50KHz Current 9mA Main board power system LM2596S-5, 12V to 5V (3A SPEC) To CPU, Eeprom, 24c21, control-inverter-on.off 860mA when Cable not Connected 841mA when Normal operation AIC1084, 5V to 3.3V (5A SPEC)

  • Page 55: Pcb Layout

    PCB LAYOUT...
  • Page 56 CN302 C383FA-1 +3.3V VDDA CN201 RVDDA U200 TCLK1 +3.3V R230 PCLK TCLK (NC) C206 8 7 6 5 TCLK 22UF C207 C208 C209 C210 C211 C212 C213 RP300 PDISPE PD47 PD47 (Panel-Select) PD46 LP202 LP201 PD46 PD45 U302 HDATA0 PD13 PD13-1 PD14 PD14-1...
  • Page 57 CN302 C383FA-1 U200 8 7 6 5 RP300 (Panel-Select) HDATA0 U302 R320 R322 R324 HDATA 8XC51/PLCC MFB7 (NC) (NC) (NC) MFB7 HDATA0 T2/P1.0 P2.0/A8 MFB8 MFB8 MFB7 T2EX/P1.1 P2.1/A9 MFB9 MFB9 MFB8 P2.2/A10 P1.2 R321 R323 R325 MFB9 P1.3 P2.3/A11 (NC) (NC) (NC)
  • Page 58 +3.3V VDDA RVDDA U200 TCLK1 +3.3V R230 TCLK (NC) C206 8 7 6 5 TCLK C207 C208 C209 C210 22UF RP300 PD47 PD47 PD46 PD46 PD45 HDATA0 PD45 HDATA C216 C217 C218 C219 C220 PD44 22UF MFB7 PD44 MFB7 PD43 PD43 MFB8 MFB8...
  • Page 59 CN201 TCLK1 +3.3V R230 PCLK TCLK (NC) C206 TCLK C207 C208 C209 C210 C211 C212 C213 22UF PDISPE PD47 PD47 PD46 LP202 LP201 PD46 PD45 PD13 PD13-1 PD14-1 PD14 PD45 C216 PD12 PD12-1 PD15 PD15-1 C217 C218 C219 C220 C221 C222 C223 PD44...

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