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TABLE 3-4.
TRACK SERVO CIRCUIT FUNCTIONS (CONT'O)
Circuit Element
Function
Oibits Detect
50
~sec
and 3
ms
delays used to prevent the track servo circuit
from being turned on by random noise spikes during a heads
un-
loaded condition or a load heads operation.
End of Travel (EOT)
Monitors integrated velocity to enable ECT circuit.
When ve-
locity inteqrator output exceeds about 1.2v, heads have moved
a distance of approximately
two
tracks without sensing any cyl-
inder pulses.
Reverse EOT
FF
Indicates that heads are positioned over outer guard band.
Refer to First Seek and RTZS discussions for further details.
Forward
EO'!' FF
Indicates that heads are positioned over inner guard band.
This is an error condition.
output is zero, as in a heads unloaded con-
dition, A33·6 is not triggered and its output
is hiqh.
This holds A3l7 at a loqic zero.
The positive and neqative qates and cylinder
detect circuits are now inhibited.
When the heads are loaded and dibits are. out-
puted from the preamp, A336 is triqqered and
retriggered, keepinq its output at a logic
zero.
This releases the timinq components
of A337 and after 3 ms its output goes to
one turninq on the Track Servo circuit.
If
dibits are lost for more than 50 usee, A336
times out and resets A337 to a loqic zero,
disabling the Track Servo circuit (See Fiq-
ure 3-30).
CYUNOEa PULSE GENERA nON
As the servo head crosses the interface of
the even/odd dibit tracks (Figure 3-31),
the servo siqnal decreases toward null. Two
operational amplifiers connect.ed as Schmitt
triggers switch state.
The hysteresis de-
signed into the circuit causes both triggers
to be up only while the servo signal is be-
tween Ov and 0.4v.
These siqnals are applied
to two level shifters (A364/A365).
Their
outputs are ANOed together to provide a 10
microsecond cylinder pulse.
Each cylinder
pulse:
1. Increments the difference counter.
2. Switches the two velocity integrators
(one each in the servo circuit and track
servo circuit) to ground.
It is possible that the last cylinder pulse
may not be generated when the seek is com-
pleted, causing the difference counter to
hang
u~
at 1022 or 510 for BR3E4/3E5.
The
On
Cyl~nder
signal provides a pulse to in-
crease the difference counter to 1023 or
511
~or
Br.3E4/3E5.
With the dif!erence
3-68
counter at 1023 or 511 for BR3E4/3ES tracks
to go equal. zero and On Cylinder is avail-
able so Positioner Busy status drops.
The track servo circuit remains active fol-
lowinq completion of a seek.
If the servo
head drifts off of its centered position,
the track servo signal will no longer be at
null.
The siqnal, functioning as the fine
servo signal within the servo circuit, will
act as a poSition error signal to drive the
positioner back into position.
MACHINE CLOCK CIRCUIT
GENERAL
The machine clock circuit uses dibits gener-
ated by the track servo circuit to generate
the basic 806 kHz clock signal.
This signal
is applied to the followinq circuits:
1. Index detection·
2. Write clock generator
3.
Sector counter
CLOCK
GENERATION
The circuits (Figure
3-32)
most important
portion is a phase locked loop
(PLL).
The
loop compares the frequency of input data
(dibits) with feedback data.
A
comparator
circuit generates a square wave input to a
GJK
circuit in the voltage controlled oscil-
lator.
(Refer to Section 6 for an explana-
tion of the
GJK
circuit.)
The
GJK
generates
a voltage proportional to the difference in
frequency between input data and feedback
data.
The output of the
GJK
is applied to
the voltage controlled oscillator to control
its frequency.
The
PLL
is satisfied when
the input and feedback frequencies are
identical.
Note that data and feedback are
90
degrees out of phase.
83318200
C
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