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The output of the differentia tor (Figure
3-48), is applied to a filter (A878) which
attenuates the third harmOnic of the low
frequency Read signal.
This effectively
lowers the resolution of the signal.
The output of the filter is amplified and
then rectified.
A capacitor is charged to
the average dc level of the rectified sig-
nal.
This voltage is then applied to the
reference input of a comparator (A886) and
the rectified signal to the other input.
When the rectified signal becomes more posi-
tive than the reference signal, the compar-
ator switches.
This produces a squarewave
output that is used as an Amplitude Enable
signal to reject noise and spurious pulses
in the address gap area.
The only time this
output is used is during a Search Address
Mark operation.
The Data Detector consists of a comparator
(A883) and a retriggerable single shot delay
(X884).
The reference voltage on the com-
parator is a fixed dc voltage of about -0.46v.
Each time the single voltage crosses the
reference, the single shot is retriggered.
The single shot will not time out as long as
data above the fixed reference is being read.
When a gap is reached, the single shot is
retriggered
by
the last bit preceding the
gap, times out for 670 nsec, then changes
state to indicate an absence of data (Figure
3-48).
The single shot is retriggered
by
the first data bit following the gap and by
each succeeding bit, indicating that data is
again present.
The Time Constant Control circuit switches
the time constants of the AGC Amplifier and
Level Detection circuits.
Switching from a
short time constant to a long time constant
avoids responding to the loss of amplitude
in the address mark gap area.
Figure 3-49
shows block and timing diagrams of the Time
Constant Control circuit with the address
mark gap in three different positions.
The Level Detector circuit is normally in a
short time constant of 5 usec in order to
rapidly respond to changes in signal ampli-
tude to maintain adequate margin in the
amplitude enable function.
The 5 usec time
is long enough so that the level detector
does not respond to drop outs caused by disk
surface bad spots.
During the address mark
gap, the level detector is switched to a
time constant of 100 usec.
This prevents a
shift in the comparator reference level so
noise in the gap area does not produce false
enable pulses.
The AGC amplifier is allowed 25 usec to
stabilize from the Head Select and Read Gate
transients.
A head may be selected and Read
Gate can come up any time during a revolu-
tion of the disk, so it is possible that the
address mark gap could occur during the 25
usec stabilizing period.
The AGC time con-
83318200
A
stant is held in the short condition for the
first 10 psec following Read Gate.
If a gap
occurs between 10 and 25
~sec,
the AGC ampli-
fier is switched to a long time constant of
200 usec to maintain a relatively constant
gain level through the gap area.
Data Latch Circuit
The Data Latch circuit (Figure 3-50) consists
of a low pass filter for the low resolution
channel and zero-cross detectors and pulse
generators for both the high and low resolu-
tion channels.
The Read Data from the differentia tor is
applied directly to the zero-cross detector
in the high resolution channel and through
the low pass filter to the zero-cross de-
tector in the low resolution channel.
As
mentioned before, the filter lowers the
resolution of the Read signal by attenuating
the third harmonic of the signal.
The pulse generators (N882 and N877) produce
pulses for each zero-crossing of the data.
By appropriate delays, the low channel pulse
(IN882) enables the K input to the output FF
(K873) in time for the high channel pulse
(N877) to clear it.
A 50 nsec output pulse
is formed when the delayed feedback resets
the FF.
The leading edge of the output pulse
retains the timing of the high resolution
channel.
Note that the propagation time of
the various gates must be considered to en-
able the K input at the proper time.
When-
ever the frequency of the read back data is
decreasing, there is a camels hump in the
differentiated output.
(See Figure 3-48).
With sufficient frequency change and high
resolution heads, the differentiated signal
may actually pass through zero.
The high
resolution channel can react to these extran-
eous zero-crossing pulses: the low cannot
because of the low pass filter.
Therefore,
they are ignored by the output FF because
it cannot be cleared unless the low channel
K enable is present.
The rejection of spurious pulses in the ad-
dress mark gap is accomplished by ANDing the
high channel pulses with an enable pulse.
During the search mode, the Amplitude Enable
pulses are passed through and ANDed with the
high channel zero crossover pulses.
When a
zero crossover pulse corresponds to an enable
pulse, it is passed through to reset the Out-
put FF.
There are noise created zero-cross-
over pulses in the address mark gap area.
However, there are no enable pulses, so the
reset input to the Output FF is disabled.
Noise pulses in the low resolution channel
are present at the set input of the FF, but
are ignored because the FF is not resetdaring
the gap period.
3-93
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