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Any of these peak shift conditions can cause
errors during subsequent
~ead
operations.
The drive compensates for these known errors
by intentionally writing a pulse earlier or
later than nominal.
This function is accom-
plished by the write compensation circuit.
Write Compensation Circuit
The write compensation circuit (Pigure
3-44)
converts
NRZ
data into
MPH
data while in-
tentionally shifting the pulses in
the
data
cell to compensate for peak shift.
Data from
SERDES
enters a decode shift re-
gister (K756 through K750) in
NRZ
format.
It is shifted through the register by a
two-phase clock siqnal consisting of Write
Clock and its inversion, Not Write Clock.
As
the data shifts through the register, the
register contents are examined by a series
of gates to analyze the bit pattern.
These
gates determine if the incoming data fre-
quency is constant (00000 or 11111),
in-
creasing (011 or 1000), or decreasing
(10 or
001).
The timing of the write data
pulses applied to the write Driver Circuits
(Pigure
3-40)
are adjusted to compensate for
the frequency shift:
o
WRITE
- ,
TOGGLE
~.
______________
~
t
I
I
I
I
I
Z£RO
,
PEAK ........
SHIFT
I
NOTE:
o
ICE~IZED
INOIVIDUAL
READ8ACK'v'Ol.TAG£S
I
I
EARLY
~PEAK
SHIFT
•
If frequency is constant, there will be
no peak shift.
An MPH Clock pulse
(pulse
at beginning of a cell) is generated
while Write Clock is down: MPH
Data~
(pulse at middle of a cell) is generated
while Write Clock is up.
The pulse,
clock or data, is intentionally delayed
by 10 nanoseconds and is applied to the
On Time Gate.
This pulse is the write
data pulse applied to the write toggle.
•
If frequency is decreasing, the apparent
readback peak (Pigure
3-43)
would occur
later than normal.
To compensate for
this, the data is written earlier than
nominal.
Early Gate is enabled.
This
causes clock/data to be written con-
currently with Write Clock or Not Write
Clock: the
10
nanosecond delay is by-
passed.
•
If frequency is increasing, apparent
readback
peak
would occur earlier than
normal.
Therefore, data is intentional-
ly written later than nominal.
Late
Gate is enabled.
This causes the write
data to be written
20
nanoseconds after
the beginning of the cell.
•
I
I
~
I
I
I
I
LATE
~PEAK
SHIFT
o
L
I
7M36 ..
Figure 3-43.
Peak
Shift
3-86
83318200
A
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