HP 26067A Manual page 18

HP-IB INTERFACE/26067B
available the I/O control circuitry will generate
WAIT signals which will hold off the I/O
processor from accessing the I/O RAM memory
until it becomes available. When the I/O RAM
memory becomes available the WAIT signal is
discontinued and the I/O processor is given access
to the I/O RAM.
To allow the I/O processor access to the I/O
RAM memory the I/O control circuitry will
enable the Gate (GATE) signal and the Direction
(DIR) signal to allow the I/O processor data to
pass through the gate to the memory. The I/O
control circuitry enables the Address Select (AS)
line to the Address Multiplexer to allow the I/O
processor address to address the memory.
Each byte is transferred from the HP-IB
processor across the bus into I/O processor and
then back onto the bus into I/O RAM. For each
byte the I/O processor selects an I/O RAM
address, outputs the address across the address bus
to write the data into the memory.
The I/O processor addresses and places the data
byte onto the bus. The I/O RAM memory will
shift the bytes into its memory when Write
Enable (WE) signal from the I/O control
circuitry becomes active.
Each byte of data received by the HP-IB
processor is transferred into memory in this
manner until all the data is transferred. When
the final data byte is received by the HP-IB
processor, the HP-IB processor enables the
EOSINT interrupt line. This indicates to the I/O
processor that the data transfer is complete.
Now the I/O processor will complete the packet
information and write it into the packet memory
location. When the data transfer operation is
complete the I/O processor will interrupt the
printer control processor to let it know that the
interface shared I/O RAM contains information
for the printer control processor.
The I/O processor interrupts the printer Control
Processor by enabling the Interrupt Master
(INTMAS) signal. Since anyone of several slaves
can enable the INTMAS signal line and the
printer control processor cannot identify which
slave has interrupted, the printer control
processor will poll the slaves one at a time to
identify the one requiring service. To identify
the interrupting slave the printer control
processor enables the Interrupt Acknowledge
(INTACK) signal line. This line is common to all
slave circuits. Any slave which interrupted the
printer control processor will respond by
enabling its Poll Acknowledge (POLACK) signal
line. Each slave circuit has its own unique
POLACK signal line which identifies to the
printer control processor the source of the
interrupt. When the printer control processor is
ready to accept data from the interface, it will
respond to the interrupt request by the interface.
For the printer control processor to communicate
with the interface the printer control processor
must access the I/O RAM and retrieve the
information (packet and data) placed there by
the I/O processor. For the printer processor to
address the I/O RAM, it must gain access to the
I/O ram in the same manner as the I/O
processor. The printer control processor will
enable its Memory Request (MEMREQ) and Read
(RD) signals to the I/O control circuitry. If the
I/O processor is not using the I/O RAM for any
operation the I/O control circuitry will allow the
printer control processor access to the I/O RAM.
For the printer control processor to access the
RAM the I/O control circuitry enables the
bi-directional bus gate A allowing the printer
control processor to access the I/O RAM across
the bus. The control circuitry will also enable
the I/O Address Multiplexer to allow the Address
Select signal to the Address Multiplexer to pass
the master address bus addresses to the I/O RAM.
Thus the data from the computer is passed
through the HP-IB interface to the printer. The
transfer of data from the printer to the
computer through the interface is identical
except the direction is reversed.
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