Video Controller Architecture; Diskette Controller, Serial Interface, Parallel Interface; Keyboard Controller; Pcmcia Controller - NEC VERSA 4000 Service Manual

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Video Controller Architecture

The video controller architecture is broken down into several modules. The five significant
modules include the sequencer, CRT controller, graphics controller, attribute controller and
dithering engine.
For example, the sequencer manages CPU and display memory timing. The CRT controller
controls sync and timing signals. The graphics controller permits the flow of communication
between the CPU data bus and the 32-bit internal data bus. The attribute controller pro-
duces a 4-bit wide video data stream that refreshes the display.

Diskette Controller, Serial Interface, Parallel Interface

The PC87334 chip is a 100-pin plastic Thin Quad Flat Plastic (TQFP) chip. The controller
changes 8-bit parallel data into serial data and writes the data to the diskette. Conversely,
the serial data is transmitted from the diskette into parallel data, where it remains until the
read operation takes place.
Additional PC8733 chip operations include:
T
ISA compatibility
T
low-power CMOS with enhanced power-down mode

Keyboard Controller

The keyboard controller (M38813E4HP) supports a PS/2-style keyboard, mouse and secu-
rity features such as keyboard hot keys and password. Refer to Appendix A for keyboard
interface connector pin assignments.
When data is written to the output buffer, the controller generates an interrupt, and requests
the CPU to receive the data. The controller automatically adds an even parity bit to the data
sent and waits for a response. The device must acknowledge that the data was successfully
received by sending a response to the controller for each byte of data received.

PCMCIA Controller

The controller (PD6722) interfaces with the ISA bus, PCMCIA card socket and configura-
tion registers to provide:
T
memory address mapping, I/O address mapping
T
power management for each PCMICA card socket, controlled through power and
RESETDRV control registers
T
the elimination of interrupt conflicts using interrupt steering.
Technical Information
1-15

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