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Triple Timer Module
Timer Modes of Operation
9.5.2
Measurement Modes
Since the measurement modes use the internal clock to increment the counter, but use
the external signal for gating the count, synchronization is needed. The synchronization
process can affect the measurement exactness by as much as a single selected internal or
prescaled clock cycle.
9.5.2.1
Mode 4—Pulse Width Measurement
The Pulse Width Measurement mode is selected when TC[3:0] is set to 0100. In this
mode, the counter is cleared after the TE bit is set. After the first appropriate transition
(as defined by the INV bit) occurring on the TIO input pin, the counter is loaded with the
TLR value on the first timer pulse derived either from the DSP internal clock (CLK)
divided by two or from the prescaled clock input. Each subsequent timer pulse
increments the counter.
When the first edge of opposite polarity occurs on TIO, the counter stops, the TCF bit in
TCSR is set, and if the TCIE bit is set, a compare interrupt is generated. The contents of
the counter is loaded into the TCR and the user's program can read its value that
represents the widths of the TIO pulse. On the first timer pulse following the next
transition that occurs on TIO input pin, the counter is loaded with the value in TLR (if
TRM is set), and the count is resumed. If the TRM bit is cleared, the counter continues to
be incremented on each timer pulse. This process is repeated until the timer is disabled.
If counter wraparound occurs, the TOF bit is set. If the TOIE bit is set, an overflow
interrupt is generated. In this mode, TIO acts as a gating signal for the internal timer
clock. The INV bit determines whether the counting is enabled when TIO is low (the INV
bit is set) or TIO is high (the INV bit is cleared).
9.5.2.2
Mode 5—Period Measurement
The Period Measurement mode is selected when TC[3:0] is set to 0101. In this mode, the
counter is cleared after the TE bit is set. After the first appropriate transition (as defined
by the INV bit) occurring on the TIO input pin, it is loaded with the TLR value on the
first timer pulse derived either from the DSP internal clock (CLK) divided by two or
from the prescaled clock input. Each subsequent timer pulse increments the counter.
On each following transition of the same polarity that occurs on TIO, the TCF bit in the
TCSR is set. If the TCIE bit is set, a compare interrupt is generated. The contents of the
counter is loaded in the TCR. The user's program can then read its value and the value in
the TCR to determine the distance between TIO edges. On the next timer pulse, the
counter is loaded with the value in the TLR (if the TRM bit is set) and the count is
resumed. If the TRM bit is cleared, the counter continues to be incremented on each
timer pulse, accumulating measurements results. This process is repeated until the timer
is disabled. If counter wraparound occurs, the TOF bit is set. If the TOIE bit is set, an
overflow interrupt is generated. The INV bit determines whether the period is measured
9-16
Freescale Semiconductor, Inc.
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
DSP56602 User's Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
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