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Freescale Semiconductor, Inc.
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
9.4.1
Timer Prescaler Load Register (TPLR)
The Timer Prescaler Load Register (TPLR) is a 16-bit read/write register that controls the
prescaler Divide Factor and the source for the prescaler input clock. The control bits are
described in the following paragraphs.
9.4.1.1
Prescaler Preload Value (PL[13:0])—Bits 0–13
The Prescaler Preload Value bits (PL[13:0]) contain the prescaler preload value. This
preload value is loaded into the prescaler counter whenever either the counter reaches
the value of 0 or the counter switches state from disabled to enabled. For PL[13:0] = N,
the prescaler counts N + 1 source clock cycles before generating a prescaled clock pulse.
Therefore, the prescaler Divide Factor is the preload value + 1.
The PL[13:0] bits are cleared by hardware and software reset .
9.4.1.2
Prescaler Source (PS[1:0])—Bits 14–15
The Prescaler Source (PS[1:0]) bits control the source of the prescaler clock. Table 9-1
summarizes the functionality of the PS bits. The DSP internal clock CLK divided by two
is selected when the PS[1:0] bits are cleared. The other combinations select one of the TIO
pins as the source clock for the prescaler, regardless of the operating mode of the
selected timer.
PS1
0
0
1
1
Notes:
1. If the prescaler source clock is external, the prescaler counter is
incremented by the transitions on the TIO pin. The external clock is
internally synchronized to the internal clock and its frequency should be
lower than the DSP internal clock (CLK) divided by 4.
2. To ensure proper functionality, the PS[1:0] bits should be changed only
when the prescaler counter is disabled.
The PS[1:0] bits are cleared by hardware and software reset.
MOTOROLA
Table 9-1 PS[1:0] Bit Functionality
PS0
0
DSP internal clock (CLK) divided by two
1
0
1
DSP56602 User's Manual
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Triple Timer Module Programming Model
Prescaler Clock Source
TIO0
TIO1
TIO2
Triple Timer Module
9-7
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