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Freescale Semiconductor, Inc.
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
Notes:
1. After the timer is enabled, the TIO pin output value is set equal to INV bit
to guarantee the correct first pin transition.
2. In this mode, the internal hardware preserves the TIO value and direction
for an additional 2.5 internal clock cycles after reset is activated, ensuring a
valid length reset when the TIO is used as input to the RESET pin.
9.5.5
Reserved Modes
Timer modes 8, 11, 12, 13, 14 and 15 are reserved.
9.5.6
Timer Behavior During WAIT and STOP Instructions
The timer clocks are active during the execution of the WAIT instruction. Thus, timer
activity continues undisturbed. On reaching the final event, if the timer interrupt is
enabled, an interrupt is generated and the processor leaves the Wait state and services
the interrupt. The timer clocks are disabled during the execution of the STOP instruction.
Thus, timer activity is stopped. In Stop mode, the TIO pins are electrically disconnected
internally. If a TIO pin is used as an input, changes that occur while in Stop mode are
ignored. To ensure proper operation, disable the timer before executing the STOP
instruction.
MOTOROLA
DSP56602 User's Manual
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Go to: www.freescale.com
Triple Timer Module
Timer Modes of Operation
9-19
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