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Freescale Semiconductor, Inc.
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
9.1
INTRODUCTION
This section describes the triple timer module, composed of a common 14-bit prescaler
and three independent and identical general purpose 16-bit timer/event counters, each
with its own memory-mapped register set.
Each timer can use internal or external clocking and can interrupt the DSP after a
specified number of events (clocks) or can signal an external device after counting
internal events. Each timer connects to the external world through one bidirectional pin,
TIO. When the TIO pin is configured as an input, the timer functions as an external event
counter or measures external pulse width/signal period. When the TIO pin is used as an
output, the timer functions as either a timer, a watchdog, or a Pulse Width Modulator
(PWM) . When the TIO pin is not used by the timer, it can be configured as a General
Purpose I/O (GPIO) pin.
9.2
TRIPLE TIMER MODULE ARCHITECTURE
The triple timer module includes a 16-bit Timer Prescaler Load Register (TPLR), a 16-bit
Timer Prescaler Count Register (TPCR), a 14-bit Prescaler Counter, and three timers.
Each one of the three timers can use the Prescaler Clock as its clock source.
The Timer Prescaler Load Register (TPLR) is a 16-bit read/write register that controls the
Prescaler Divide Factor and the source for the prescaler input clock. The Timer Prescaler
Count Register (TPCR) is a 16-bit read-only register that reflects the current value in the
prescaler counter. The register bits are described in the following paragraphs. The 14-bit
Prescaler Counter is decremented on each rising edge of the prescaler input clock pulse.
The counter is enabled when at least one of the three timers is both enabled and is using
the prescaler output as its source. Figure 9-1 shows a block diagram of the triple timer
module.
MOTOROLA
DSP56602 User's Manual
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Triple Timer Module
Introduction
9-3
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