Motorola A920 Service Manual page 54

A920: GSM RX Back End (Magic LV)
RX_I
RX_I_X
GSM
DET_FLAG
RX
Front End
RX_Q
RX_Q_X
Description
The MAGIC_LV (U500) handles the backend processing for the EGSM, DCS and PCS (VLIF: RX_I, RX_I_X, RX_Q, and RX_Q_X) signal lines from LIFE. Simply,
the MAGIC_LV performs an analog to digital conversion of I /Q and sends it to the data to the board processor (POG) via the SSI (serial synchronous interface).
The MAGIC_LV also has a programmable and phase-able digital IF to improve image rejection.
In MAGICLV, each channel is comprised of a Post Mixer Amplifier (PMA), an integrated passive two pole filter, a gain stage (AMP1) followed by an active programma-
ble 2 pole anti-aliasing filter (mainly required to meet the blocking specs). This is followed by a lowpass sigma-delta ADC with a programmable oversampling clock
OVSCLK (derived from the reference oscillator) equal to 13MHz for 200kHz channel spacing (13bits).
Digital detector circuits are placed on each channel at the output of the sigma delta converters. The outputs of these detectors are compared against a level defined by
DET_LVL. If either of the detected levels exceeds the programmed threshold then the pin DET_FLAG is set high. This indicates that the signal level is excessively high
for the sigma delta modulator. DET_FLAG is read by the processor, which will respond by re-programming one of the AGC settings to a lower gain until DET_FLAG
returns low.
The outputs of the sigma-delta modulators are digitally processed through a noise cancellation circuit, comb and decimation filters. A second programmable digital LO
based on a look up ROM generates digital quadrature oscillators with programmable gain/phase correction (called balanced complex multiplier) to digitally downconvert
the I/Q signals to baseband (digital zero IF) through four quadrature mixers that provide image rejection of adjacent/alternate channels. Gain/ Phase correction at a single
baseband frequency is performed on the Digital Quadrature Oscillator to compensate the analog gain/phase mismatch of the quadrature I and Q paths. After baseband
downconversion and image reduction, the quadrature I and Q signals are further processed by digital filters that perform channel selectivity and out of band noise rejec-
tion.
A serial bus consisting of SDFS and SDRX will transmit the RXI and RXQ data in 2's complement format. BDR and BFSR are outputs from MAGIC LV. BFSR is a
framing signal which marks the beginning of an I,Q transfer. BDR is the serial data. The clock used for the serial transfer is BCLKR. When NB_RX_ACQ goes high
MAGIC LV will activate the SSI interface in the digital receiver section. The data transmission over the serial bus will begin at the next normal occurrence of valid I and
Q data, as defined internally to the digital receiver.
Anti-
Σ∆
PMA IFA
Aliasing
filter
DET
Anti-
Σ∆
PMA IFA
Aliasing
filter
MAGIC LV
U500
(RX Section)
Balanced
Complex
Filter
Prgmable
Mod
Dig CH Sel
and
Complex
IF Notch
or
Highpass
Filter
Dig Quad
Osc
BFSR
RX BDR
Serial
NB_RX_ACQ
Interface
BCLKR