Motorola A920 Service Manual page 88

A920: POG
Magic LV
(GSM)
Harmony
Lite
(WCDMA)
Description
The POG(baseband processor) integrates a 32-bit RISC Communications Engine (MCU), a 32-bit DSP Core and an Interprocessor Communications Module (IPCM)
along with associated peripherals and co-processors. The following provides a brief description of the cores and associated peripherals being used in this design.
·MCU – Micro Controller
·DSP for GSM Signal processing
·EIM(external interface module) interfaces to FLASH and DRAM
·USB/Serial Communications
·GPIO - For A/Ds
·IPCM which provides a multichannel DMA between the Mcore, DSP and peripherals.
·WCSP Interface
·GQSPI - PCAP Interface
·EBIF(External Bus Interface) DMA – WCDMA Data Transportation
·MQSPI1(Qued Serial Peripheral Interface) – WCDMA Control Signals
In addition to POG's internal memory system, the architecture provides 128Mbits (16M byte) of external flash memory via two Intel Danali 64M bit parts. The memory
bus is 23 address bits and 32 data bits. The flash memory runs at 42-45MHz.
Keypad
EL1T2
MQSPI2
Serial BBIF
DSP
Starcore
CKIH
EL1T1
MQSPI1
EBIF
WCSP
JTAG
ASAP
PCAP Codec
VSAP
1-wire
USB
IPCM
RISC
MCU
M341
MDI
cache
80kB
POG
eDRAM
Nexus GPIO
LCD
Misc
·EL1T1(Enhance Layer Timer) – WCDMA Event timer
·CKIH - WCDMA 15.36MHz clock
·GPS Interface
·USIM interface
·ASAP interface for PCAP and Bluetooth audio interface
·Serial BBIF(Baseband Interface) – GSM Data Transportation
·MQSPI2(Qued Serial Peripheral Interface) – GSM Control Signals
·EL1T2(Enhance Layer Timer) – GSM Event timer
·CKIH - GSM 13MHz clock
Helen
Mux
UART1
IrDA
UART2
GPS
UART3
128Mbit
EIM
FLASH
64Mbit
SDRAM
SDRAM
GQSPI
PCAP
MMC
SIM USIM