Motorola A920 Service Manual page 70

A920: Harmony Lite (Control Section)
Description
There are several functions that the sequence manager is controlling.
1. Sequence manager outputs to external devices
2. On/Off control of clocks, battery save signals etc...
3. Clock frequency selection for correction paths
4. DCOC register selection coarse, medium and fine modes
The HARMONY LITE has two sets of SPI interfaces; one set is for handling the control interface for the transceiver (AUXSPI lines) and ones for interfacing with POG
(SPI lines). Further, all SPI interface is generated from POG and written to HARMONY_LITE or parsed through to the MAXIM (U200 & U310) parts.
Layer one timing signals control the functionality of the RF section of the transceiver relative to the air interface. There are three signals defined on each transmit and
receive section of the transceiver. TX_PRE_KEY and RX_ON are asserted before the need to receive or transmit in order to launch the necessary sequence of events to
warm up the required functional blocks. TX_RAMP and RX_AQUIRE are asserted when actual transmission and reception are to begin. RX_SLOT and TX_SLOT are
used during continuous transmission and reception to trigger events that must be aligned with slot boundaries. It's important to reiterate, the TX_RAMP directly corre-
sponds to the PA turning on and RX_AQUIRE corresponds to data being sent to the WCSP.
Harmony Lite(U101)-Logic Section
2361LOCK GPI_1
2361_SHDN
SMO_15
TX_STBY*
SMO_21
2361_CS* WB_ASPI_CE_2
HL_TX_EN SMO_9
V_DETECTOR SMO_23
VGC1
WCDMA
VGC2
TX
VLOAD_SW
PABIAS1
PABIAS2
RF_DETECT
MUX
TEMP_COMP
ASPI_DATA
ASPI_CLK
MAX2388_SHDN
WCDMA
MAX2309_LOCK
RX
MAX2309_SHDN
RX_STBY*
MAX2309_CS
WB_TX_RAMP
RF_RESET*
PORB
SPI_CE
HARMONY_CS
SPI_DATA_IN WB_SPI_MOSI
SPI_DATA_OUT WB_SPI_MISO
SPI/
WB_SPI_CLK
Sequence
WB_RX_ON
Manager
WB_RX_SLOT
WB_RX_ACQ
WB_TX_PRE_KEY
WB_TX_SLOT
AOC_PWR_UP_DOWN
WCSP
POG