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CJT~JTS
II';
F'~
- 5
, - - - - - - - - - - -
INPUT
9's COMPLEMENT
Digit
1
2
4
8
1
2
4
8
a
L
L
L
L
H
L
L
H
1
H
L
L
L
L
L
L
H
2
L
H
L
L
H
H
H
L
3
H
H
L
L
L
H
H
L
4
L
L
H
L
H
L
H
L
5
H
L
H
L
L
L
H
L
6
L
H
H
L
H
H
L
L
7
H
H
H
L
L
H
L
L
8
L
L
L
H
H
L
L
L
9
H
L
L
H
L
L
L
L
INPUT
DECIMAL OUTPUT
12
13
14
15
1
2
3
4
5
6
7
9
10
11
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
L
H
H
H
H
H
H
H
L
L
H
H
H
H
H
L
H
H
H
H
H
H
L
H
L
L
H
H
H
H
L
H
H
H
H
H
L
H
L
H
H
H
H
H
H
L
H
H
H
H
L
H
H
L
H
H
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
NOTE 5: On A221C1, input at pin 12 is hard wired low, and output
pins9, 1a,and 11 are not used IN/C).
NOTE 4: 9's Complement Circuitry:
CODE
Digit
1 2 4 8
a
a a a a
1
1 a a a
2
a
1
a a
3
1 1 a a
4
a a 1 a
5
1 a
1
a
6
a 1 1 a
7
1 1 1 a
8
a a a 1
9
1 a a 1
H
+5 V
L
a
V
H Delay Flag - indicates the delay flag line should be
+
5 V
when a delay flag signal is present.
POSITIVE LOGIC
I)'· (IA'18"le)
+
(ID'IE'IF)
Zf '
(2A.28)
+
i
2C.20)
2 A
28
2C
L Data Valid - indicates the data valid line should be 0 V when
a data valid signal is present.
L
NOTE 3: BCD Low true logic, switch contact(s) to ground is true
state.
In Local Mode (A Low, B High) the input on pins 9 and 10 is
inverted and applied to pin 8. The input on pin 5 is inverted and
applied to pin 6.
NOTE 2: In Remote Mode IA High, B Low) the input on pins 12
and 13 is inverted and applied to pin 8. The input on pin 3 is
inverted and applied to pin 6.
Example:
NOTE 1: Logic signal levels are shown
by
the letters H or L
preceding the name of the line. The Hand L indicates the true state
(signal present). Voltage levels for the Hand L are:
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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