HP 3320A Operating And Service Manual page 129

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Example:
H Oelay Flag - indicates the delay flag line should be + 5 V
when a delay flag signal is present.
NOTE 1: Logic signal levels are shown by the letters H or L
preceding the name of the line. The Hand L indicates the true state
(signal present), Voltage levels for the Hand L are:
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H
L
+5V
OV
BCD
IC PINS
WIRED
OUTPUT
IC28 2 +5V
- 6
3,5,12 t
IC4
Clear VERN OUT
Input Data A2, 82, C2, and D2 is numerical data from shift registers
IC8-IC11.
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L Data Valid - indicates the data valid line should be 0 V when
a data valid signal is present.
NOTE 2: IC8-IC11 are 4-bit Shift Registers. The mode of
operation is controlled by the voltage level on mode control line,
pin 6. When the mode control line is high
(~+5
VI, the registers are
reset by parallel loading of Inputs A, B, C and O. Inputs A, B, C and
D are hard-wired to +5 V. When the mode control line is low
(;::::;:0 V) the Serial Input, pin 1, is enabled. These IC's are connected
for serial-ta-parallel conversion of the numerical data bits, bl-b4.
The "A" output of each
Ie
represents the least significant digit. The
"0" output of each IC represents the most significant digit.
POSITIVE
_OG:C
,
,
o
,
, ,
NOTES
I. l n'81TTIMEBEFORE
CLOCK PULSE
2"0 +1'8IT TIME AFTER
CLOCI( PULSE
3, ':'.00 MEANS OUTPUTS DO NOT CHANGE
STATES WITH CLOCK PULSE
4,Q'Q o MEANS OUTPUTS (HANGE STATES
Wn.. C_OCI<: PULSE
Low input to Cloar sets
Q
to logical O.
Clear i. independent of Clock
NOTE 4: Logic diagram of IC is shown below.
J MCJ( C_JCK
I~PUT CONTRO·~
BCD
IC PINS
WIRED OUTPUT
IC18 5,12
+5V 3
2,3
W
IC19
2,5,12 +5 V 2
3 t
IC20-IC22 2,3,5,12 +5V
0
IC23 2,3,5 +5V 8
12
t
IC25-IC26 2,3,5,12 +5 V
0
IC27 3,5 +5V
9
2,12
t
Input data A1, 81, C1, and Dl is hardwired, as listed below, for the
"initial turn on conditions" listed in Section III.
All inputs and outputs are low true.
NOTE 3: IC18-IC23, and IC25-IC28 are 4-bit Data Selectors/
Storage Registers (latches). All inputs and outputs are BCD, low
true. When L Clear IOata Seiectl input is low (""0 VI, input data
Al, 81, Cl, and D1 is applied to the respective outputs QA. QS'
QC' and QO' When Data Select input is high, input data A2, B2, C2
ana 02 is applied to the respective outputs. The selected input data
is shifted to the output terminals on the negative-going edge of
clock pulse.
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