HP 3320A Operating And Service Manual page 135

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Low input to Clt.r •• " Qt. lotlc.1 O.
Cltor is indoponde"t of Clock
OUTPUT:C 21
1;2
Local mode A Low, B High
Remote mode A High, BLow
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NOTE 5: Logic Diagram of
Ie is shown below.
NOTE
4: Local/Remote select lines from A24 Assembly:
NOTE 3: (CONrO.)
TO XA23A
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Par! No. 03320-66523
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I COMPON ENT 22
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POSITIVE LOGIC iY_(IA·IS·IC)+:ID·IE·IF)
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(ZA.2B)
+ (
2C.20)
L Data Valid - indicates the data valid line should be 0 V when
a data valid signal is present.
H Delay Flag - indicates the delay flag line should be
+
5 V
when a delay flag signal is present.
H = +5 V
L
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0 V
TOW2JI
I COMPONENT 4749
:2 CIRCUIT 4850
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In Local Mode (A Low, B High) the input on pins 9 and 10 is
inverted and applied to pin 8. The input on pin 5 is inverted and
applied to pin 6.
IC 18 IF 1£ 10 IY
NOTE 3: Logic diagram of IC is shown below.
Example.:
NOTE 2: In Remote Mode (A High, B Lowl the input on pins 12
and 13 is inverted and applied to pin 8. The input on pin 3 is
inverted and applied to pin 6.
NOTE 1: Logic signal levels are shown by the letters H or L
preceding the name of the line. The H and L indicates the true state
(signal present). Voltage levels for the Hand L are:
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