Toshiba D-VR3SU Service Manual page 145

(3) Tuner Block
A. Low pass filter & high pass filter
This consists of IF trap circuit and UHF & VHF separation circuit. If the input signal is IF(45.75MHz), this filter
prevents interference.
B. Single tune & RF AMP
This consists of a filter circuit, RF AMP, impedance conversion circuit, image trap and a single tuning circuit. It
prevents noise and other interference signals. RF AMP is controlled by AGC come from IF DEMOD block.
C. Double tune
It consists of a double tuning circuit to improve rejection characteristic which results in a better band characteris-
tic.
D. MOP IC (Mixer, OSC, PLL)
It consists a VHS and UHF OSC and mixer circuit. We applied a double balance mixer to have better rejection
characteristic, it shows especially various beat characteristic.
It serects channels and contains charge pump band driver. The minimum step standard frequency 31.25KHZ.
L.P.F
FROM
MD SECTION
MOP IC
! SONY : CSA3250AN
@ T I
: SN761672A
S.T(VL)
H.P.F
+
IF trap V.RF Amp
S.T(VL)
H.P.F S.T(U) U.RF Amp
AGC
from IF Section
Fig. 7-30 Tuner Section Block Diagram
D.T(VL)
MOP IC
CXA3250AN (SONY)
SN761672A (TEXAS Instruments)
D.T(VH)
VHF
OSD
D.T(U)
UHF
OSD
LPF
Tu voltage
out
Fsc IN
Circuit Operating Descriptions
V.MIX
U.MIX
IF
OSC
AMP
AMP
Prescaler
to IF Section
C.P.
BAND SW
REF
Tu Clock Data +B
IF S.T
IF
VL
VH
U
7-45