Motorola APX 7000 Detailed Service Manual page 71

Theory of Operation
: Controller
3.2.4.10.8 UARTs
Two of OMAP's UARTs are configured for peripheral interfacing.
The four-wire UART1, which is capable of hardware flow control, is available on the side connector
for accessory devices. The signals are level translated via MAKO and routed to the side connector
via J4001. Pin-outs of the UART signals on the side connector is shown in
and Table 7-11 on page
OMAP's UART2, which is a two wire interface, capable of software flow control only, is connected to
the GPS receiver IC on the expansion board. The signals are routed to the expansion board via
J4001.
3.2.4.10.9 CPLD (U6101)
The CoolRunner IC is a complex programmable logic device (CPLD) programmed specifically for the
APX 7000/ APX 7000XE product line. The CoolRunner IC is flash based and comes pre-
programmed. It is contained in an 8x8mm, 132 BGA package with 0.5mm ball spacing. The primary
functions of the CPLD are clock generation, GPIO expansion, SSI clock and frame sync direction
control, F2 multiplexing, secure data control, main display off-loading and clock inversion.
The MAKO IC supplies the CPLD's 1.875 V core voltage and a 24.576 MHz reference clock. The
1.875 V core voltage is used for internal logic and I/O buffers. MAKO's 24.576 MHz clock source is
used to generate a 32.768 kHz clock for OMAP booting, Real Time Clock / timer, and for GPS. It is
also used to generate 4.096 MHz for the MACE IC.
The CPLD is controlled through OMAP's EMIFS interface. It supports 31 configurable GPIOs. It also
supports 20 input only pins that are accessible through an EMIFS read operation. Some of the
GPIOs supported by the CPLD include GCAI_GPIO_0, F2_PARAMP_MON, and USB_CURR_LIM.
Some examples of the inputs the CPLD is programmed to support are some of the top and side
controls buttons (SEC_CLEAR, FREQ_SEL, MON, SIDE_1, SIDE_2, and TG0) and board ID. See
Table 7-14 on page 7-33
CPLD interfaces.
OMAP 1710
Processor
7-9.
for a complete list of pin assignments.
MAKO
F2 Select
F2 Timer
KEYLD_MISSING
GCAI GPIO0
Figure 3-37. CPLD Block Diagram
24MHz
CPLD
EMIFS
KL_SWITCH
Figure 3-49, on page 3-60
Figure 3-37 below shows the basic
4.096MHz to MACE
32kHz to GPS
32kHz to OMAP
GPIOs
GPIs
3-47