Motorola APX 7000 Detailed Service Manual page 76

Theory of Operation
3-52 : Controller
Figure 3-42. Display Circuit Detail Overview Block Diagram (VOCON Board MNCN6202/ MNCN6203)
All the LCD control lines for the RGB I/F (Pixel Clock, Vsync, Hsync, Output Enable), must be
running prior to initializing the external LCD Driver via SPI. The timing of these control signals and
the 18-bit data bus (LCD_PIX0 to LCD_PIX17) is crucial and a sample timing diagram is detailed in
the waveform section. The pixel clock is used by the LCD driver IC as the master clock to control
timing internal to the IC and is the main timing of the pixel data. The LCD_VSYNC is the vertical
synchronization and signifies the end of each frame of data sent to the display, and its data rate is
just above 60 Hz. The LCD_HSYNC is the horizontal synchronization signal and is used to signify
the end of the row, and its frequency is around 22 kHz. The LCD_OE signal is the output enable and
indicates to the LCD driver when valid data is present on the bus. These signals are generated in the
OMAP IC and are routed through resistors on the VOCON board (see Chapter 5 "Troubleshooting
Charts" for resistor description) prior to passing through the keypad flex to the LCD module.
The QVGA LCD Module operates in continuous and internal self-refresh modes. The internal refresh
of the display is initiated by setting Output Enable (LCD_OE) high after sending 1 entire frame or
more to the display via the RGB interface. The LCD Driver has internal GRAM, such that it can
continuously refresh the screen contents. The output enable line (LCD_AC) is routed through the
CPLD, as shown in Figure 3-41, to guarantee the appropriate switching time while using internal
circuitry between these modes. Basically, the display data will be sent to the module at a rate of
5 times per second as opposed to the LCD Driver's output frame rate to the display of 60 Hz. This
solution results in a reduction in data on the traffic controller bus, which lightens the loading on
OMAP.
The QVGA (72012006002) display uses the 16-bit Special optimized Screen Interface (SoSSI) for
data and commands used a Specially-Optimised Screen Interface (SoSSI) which required control
lines from the OMAP (SoSSI.CS, SoSSI.CMD, SoSSI.RD, SoSSI.WR) to send the data and image to
the display. The QVGA (72012006002) LCD Module operates using VCC_2.775D (2.775V) and
VCC_SW_1.875(1.875V).
An 16-bit parallel bus is used for data and command communication between OMAP's SoSSI
interface and LCD driver IC. The F_DISP_DATA_CMD signal indicated the type of data being sent to
the driver. A '0' corresponds to command data and a '1' corresponds to display data. Data only
travels in one direction, from OMAP to display driver. Therefore, the F_DISP_RW line will always be
low. Display data is latched on the falling edge of the F_DISP_RW_EN signal. Data only travels in
one direction, from OMAP to display driver. Therefore F_DISP_RW line will always be low. Display
data is latched on the falling edge of the F_DISP_RW_EN signal.
The SoSSI interface uses the LCD DMA controller/bus to allow the LCD module to access system
memory. Therefore, the transfer of pixel data process will require less CPU processing power. An
initiate DMA transfer command is used and display data is transferred to the LCD module
automatically without intervention thus offloading the processor.
Prior to the LCD interpreting any commands, the correct display power-up sequence must be
initiated. First the VCC_SW_1.875 (1.875 V) and VCC_2.775D (2.775 V) supplies must be at 90% or
above threshold and stable for 1 ms, then reset can be asserted high. After OMAP generates the
reset out signal (LCD_RST) for the display, the LCD control signals can be sent.
The QVGA LCD module is only intended to operate up to +70°C, and can become permanently
damaged if the display is subjected to operational temperatures beyond this value; thus, a
temperature cut-off circuit is implemented on the VOCON board to shutoff the display at
temperatures above 70°C–75°C. The display will turn on again 3 minutes after the temperature
stabilizes below 70°C. The temperature sensor, U6410, for the display cut-off is located near the RF
board and is input into Mako A/D Channel 7, pin K12.