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This manual describes the setup and operation of the S5U13T04P00C100 reference board. This reference board is designed as an evaluation platform for the S1D13T04 EPD Timing Controller. The S5U13T04P00C100 reference board has a host interface connector, EPD panel connector, and a 2.0 inch EPD panel.
S1D13T04 Panel HVDD Power CNF0 RVDD JP3/JP4 Figure 3-1 S5U13T04P00C100 Reference Board Block Diagram CNF0 is configured with jumpers JP3 and JP4 as shown in the following table. Table 3-1 CNF0 Configuration Selection CNF0 Comments Open Short H_RDY signal is all ways driven (Default)
Page 7 Connectors The S5U13T04P00C100 reference board has four connectors for Host Interface, Panel Interface, Power and Reserved for Production Test (J1, J2, J3 and J4). The location of these connectors is shown in the following figure. Figure 4-1 S5U13T04P00C100 Reference Board Top View / Connector Locations...
EPD VST Charge Pump C15M VCOM_PANEL EPD VCOM Capacitor J2 Power Connector Power for the S5U13T04P00C100 Evaluation Board is supplied through J2. Table 4-2 J2 Panel Interface Connector Pin No. Signal Name Description Power supply +3.0V Ground S5U13T04P00C100 Evaluation Board User Manual XA3A-G-001-00 Revision 1.0...
0 = Reset is active 1 = Reset is inactive Power Ground J4 Production Test Connector J4 is reserved for Production Testing and should not be used. XA3A-G-001-00 S5U13T04P00C100 Evaluation Board User Manual Issue Date: 2013/03/15 Revision 1.0 Seiko Epson Corporation...