Motorola EVB555 Quick Reference page 31

Pin MPC pin Signal name
77 V19 /PORESETB
80 J2 TDO_DSDO
82 K2 TDI_DSDI
83 K1 TMS
85 J1 TCK_DSCK
86 U1 TSIZ0
87 J3 /TRSTB
88 T3 TSIZ1
89 V20 /SRESETB
90 U17 /RSTCONF_TEXP
94 K3 FRZ_/PTR
25, 43,
65, 68,
GND
81, 91,
95, 97
EVB555
Quick Reference
Description corresponding to the data sheet
Power on reset: activated as a result of a voltage failure. The internal /
PORESET is asserted only if /PORESET is asserted > 100 ns.
Test data out, development serial data output:
the data-out line of the debug port interface.
Test data in, development serial data input :
The data-in line for the debug port interface.
Test mode select
Test clock, development serial clock: clock for the debug interface.
Transfer size: indicates the size of the requested data transfer.
Test reset: asynchronous reset to the test logic.
Transfer size: indicates the size of the requested data transfer.
Soft reset: after negation of /SRESET is detected, a 16-cycle period is
taken before testing an external reset. An external pull-up device is
required to negate /SRESET.
Reset configuration (input): the reset configuration mode will be sampled
from the external data bus.
Timer expired (output): status of the TEXPS bit in the PLPRCR register in
the USIU.
SGPIO freeze: RCPU is in debug mode
program trace (/PTR): an instruction fetch is taking place.
Ground
MOTOROLA
A-33