Working With The Pru - Motorola EVB555 Quick Reference

5.2 Working with the PRU

The port replacement unit, PRU, provides 64 general purpose I/O lines to compensate
the loss of the I/O pins used for the external bus interface.
The EPLD controls the PRU and decodes the addresses for the two groups of I/O
channels (A_PIO[0..31] and B_PIO[0..31]). The direction (input or output) of the I/O
lines can be configured by setting the corresponding bits PRU_CONF register of the
EPLD (see Table 5-1). If a configuration bit is set to "0" the port is used for output
whereas a value of "1" means that the port is used for input..
The value of an I/O line defined as input is read from address PRU_DATA1 (for
A_PIO[0..31]) or PRU_DATA2 (for B_PIO[0..31]). The EPLD drives the PRU to put the
values of all 32 bits per group on the bus.
For setting output values, data is written to address PRU_DATA1 or PRU_DATA2 and
latched to the output ports. If a PRU read operation follows, the previously written val-
ues are read in again from the ports working as outputs.
In Figure 5-3 the principle of the address decoding is shown.
A0
external RAM
PRU
ETK Piggyback
Host
Communication
Extension
EVB555
Quick Reference
Configuration bit no.
0
1
2
3
4
5
6
7
Table 5-1 Allocation of the configuration bits
A7A8 A15
xx00
xx01
0000
0000
0000
0001
0001
xx10
xx11
Figure 5-3 Address decoding by EPLD
I/O lines
A_PIO[24..31]
A_PIO[16..24]
A_PIO[8..15]
A_PIO[0..7]
B_PIO[24..31]
B_PIO[16..24]
B_PIO[8..15]
B_PIO[0..7]
A28 A31
0000
PRU_CONF
0100
PRU_DATA1
1000
PRU_DATA2
0000
EPLD Version
1100
Vpp12 Control
MOTOROLA
5-25