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3-2
Attention:
In
order
to
prevent
damage
to the battery
by complete
discharge, the
BATTERY
switch
must
be
set
to
OFF,
if
the instrument
will
not be used
for
approx.
3
months
or
more.
If
the battery
was
completely
discharged
by
mistake
it
can only be loaded
by
desoldering
from
the
p.c.b.
and
separate
loading.
Damaged
batteries
must
be
replaced.
During
normal
operation the battery
is
charged
from
the
+5
V
supply
via
diode 401 and
resistor
611
,
with power
off
diode 401
blo
cks
th e current
and only
the
ICs
303 and 313
will
be supplied
by
the
batta-
ry. Gate
303
keeps
the
lines
MRD
and
MWR
in
a state
that
no
information
in
the
circuit
is
destroyed
.
The
low
voltage detector
321
contains
a
comparator which
switches the
output
pin
4
to
'high'
when
the
supply
voltage
is
decreased
below
+4.2;
this
switching
level
is
determined
by
the
resistors
614 and
616.
During normal
operation the
low
voltage detector enables
the address
decoder
320
and
the pro-
cessor,
in
the
moment
of
power
off
they
are disables
immediately.
By
means
of the solder switches
A
and B
the input
line
SID
is
fixed to
'low'
in
order to avoid
distur-
bances
because
this
input
is
not
used.
A
further part
on
unit
1
is
the
lEC-bus
interface
comprising the
bi-directional
bus
drivers
301,
304-,
308
and
314
for
signal
connections
to the
I
EC
bus and
the
I
EC
bus
controller
305
which
performs
the
data
transfer,
handshake procedure and
control functions.
The
switches
842
-
844
at
the
rear
of
the
instrument
serve for
setting
the
I
EC
bus
address. Shift
register
315
senses
the
states
of
the switches
via the
parallel
inputs
and
gives this
Information
via
the
serial
output
to
the
serial
address
input,
ISR
of
1C
305.
When
a
data
transfer
via
the
I
EC
bus
is
started,
1C
305
has to detect
whether
information
received
address corresponds
to the
address
set
by
switches
842
-
844, the
data
transfer
via
buffers
309/310
is
enabled
by means
of the
signal
ODVD
attached with
signal
RD
and
the enable
line
from
the
address-
decoder
320.
The
local/remote
signal
from
1C
305
is
sent
via
the buffer
309 and
the
NOR-gate 307
to the
trap-input of the processor.
Capacitor
504
and
resistor
601
effect that
during
change
from
local
to remote only one
short pulse
is
fed to the trap input; the
diode
402
clips
negative pulses originated
by
this
capacitor.
The
solder
switch
F
serves for test
purposes
only;
the switch being
open
blocks the
data
transfer
from
the
I
EC
bus
to
the data bus of the
processor.
The
Diode
403
and
capacitor
507 between
the
clear
output
OCLR,
305.33,
and
the Input
RST
6.5
of the
processor lengthens the
clear
pulse of the
controller.
The
3
MHz
clock supply
on
unit
1
is
performed with
the
'elk
out'
signal
of
the
processor.
The
clock
is
divided to
1.5
MHz
for
the
I
EC
bus
controller
and
the address
shift register
and
to
30
kHz
for
the
timer
input.
Clock
division
is
done by
the counter 302.
All general
and
detailed
information
about
functions
and
fault
finding
in
the
lEC
bus system can be
found
In
the
'Philips
Instrumentation
System
Reference Manual',
9499 997
00411.
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