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3-12
3.5.3.
Programmable
divider
and
Phase-locked loop
The
programmable
divider
comprises
divider
1,
HEF
4751,
pos.
301/U2, and two
prescalers
303,
3C5..
RF-U2,
assisted
by
flip-flop
304.
The
operation of these
fast
prescalers
is
based
on
the
'pulse
swallov^*'
principle,
see
appendix.
They
are
switched
between
division
factor
10 and
11
by
the
signals
FBI
anci
FB2,
whereby
SY
acts as
synchronizing
signal.
FBI
FB2*1
FF
10kHz
+
9.5
V
--+0.5V
*1
The
feedback
signals
FBI and
FB2
to the
prescaler/
RF-U2
are
dependent on
the
selected
RF
frequency;
100 kHz,
10
kHz
and
1
kHz
=
or
/=
0, see table,
e.g.
frequency
setting
340.xxx
MHz.
Freq.
(MHz)
FB1
FB2
I
SY
340.000
"
I
M
340.100
-
inr IRT
340.01
X
m
-
mr
340.1
lx
inr
w
w
Fig.
8
Unit
2,
Timing diagram
HEF
4751,
selected
frequency 340.1 19
MHz
The
division factor
N
is
set
between 50.000 and 220.000 by
the
6
prog, inputs
AO
...
A3,
B2,
B3
in
BCD
code
In
a
bit parallel, digit-serial
format. Divider
1
provides
a fast
output
signal
FF
at
output
27, which
can have
a
phase
jitter
of ±1
system
input period, to allow
fast
frequency
locking.
The
slow
output
signal
FS
at
output
25,
which
is
jitterfree,
is
used
for fine
phase
control
at a
lower
speed.
The
5
MHz
X-tal
frequency
is
divided
by
the
internal divider
—set
to
500
:
1
at
the
prog, inputs
—
to the
fast
10
kHz
reference
frequency.
The
outputs
PC
1
('fine'
/
analog phase
comparator
output)
and PC2
{'coarse'
/
digital
phase
comparator
output)
are
coupled
to
an
active
low-pass
filter
315/RF-U2.
For
improved
reaction
time
two
speed-up
capacitors
are inserted into
the low-pass
section.
The
maxi-
mum
control speed
at
the outputs
is
0.1
V/ms.
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