Philips PM 5390 Service Manual page 13

Rf
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3-4
AO'
-
A5'
of port
3,
1C
309,
control
the
programmable
divider
1.
Conversion
from
TTL-
to
CMOS-
level
is
achieved
by AND-gates 302
and 306,
the outputs of
which
are
connected
via
the pull-up
sistor
network 601
to
+10
V.
These 10
V
are
generated
at
the reference
diode
401 and
the
resistor
604
from
the 12
V
supply.
At
the outputs
FB2, SY, FBI
the
+10
V
are
converted
to
ECL
levels
for
th^
1
0/1
1 :1
prescalers
on RF-U2:
9.5
V
for high, 8.2 for
low
level.
The
frequency
of
the
main
oscillator
VC01,
mixed
with
VC02
to
50
MHz
-
220
MHz,
is
divided to
provide 2
control
signals
for
the phase
comparator
within 1C 314;
a
fast
10
kHz
control
output
FF
for
fast frequency
locking
and
a
slow
1
kHz
control
output
FS
for fine
phase
control.
The
division factor
50
000
-
220 000
is
set
by 6
ports
AO'
-
A5',
BCD
coded,
in
a bit-parallel, digit-serial
format.
The
second
input
of the phase
comparator
is
the
10
kHz
reference
frequency,
derived
from
the
5
MHz
oscillator
via the
500:1
divider
within 1C 314.
The
program
clock
is
130 kHz,
derived
from
the
5
MHz
oscillator
and
the 23:1
divider
4,
!C
307.
The
division factor
23:1
is
achieved
by
connecting the outputs of
1C
30^
via
NAND-gate
31
1
to the
reset input.
The
function of the
programmable
divider
and
phase-locked loop
is
further described
in
chapter
3.5.3
with
fig.
8.
Another
function
on
unit
2
is
the
sweep ramp
generation.
The
sweep
time
divider,
binary counter
312,
counts
pulses sent
from
the timer
on
unit
1,
input
TCU. The
output
lines
are
connected
to
the
summing
point
of the operational amplifier
304
via
the
resistors
643
-
648
the values of
which
are binary
weighed
.
The
currents
through
the
resistors
generate
a
voltage
drop
a resistor
635
in
form
of
a staircase
signal.
The
output
of
!C
304
is
connected
to the
SWEEP
TIME
OUT
socket
at
the
rear
of
the instrument,
where
a
staircase
voltage
from
0
to
500
mV
in
50
steps
of
10
mV
each
is
available;
the length of
a staircase
rannp,
i.e.
the
sweep
time,
can
be
adjusted
from
0.05
s
to
20
s.
At
each
step
the
CPU
increases
the
actual
frequency by 1/50
of
A
frequency,
starting at
the
set
FRE—
QUENCY
and
ending
at
FREQUENCY
plus
A
FREQUENCY.
Sweep
is
only
possible
within
one
of the
subranges.
For
the
sweep frequency
generation
and
more
details
about
the
sweep ramp
generation
see
chapter
3.5.5.

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