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MAKING
PROGRAMMABLE
UHF COUNTERS
WHEN
NONE ARE
AVAILABLE
OR
.
.
.
PULSE
SWALLOWING
REVISITED
(Reprinted
from
Fairchild
Journal
of
Semiconductor
Progress, Vol
3,
No.
4)
Recent
developments
have aroused
greater
interest
in
VHP
and
UHF
counters
for
applications
such
as
mobile
commu-
nications
and
digitally
tuned
FM
and
TV
receivers.
Along
with
such
new
applications,
of
course,
comes
the
need
for
suitable
test
instruments
and
signal generators.
Although
these
appli-
cations
differ in
many
ways, they
have one
thing
in
common
"the need
for
high
speed
programmable
counters.
However,
it
seems
inevitable
that
for
some
applications the available
programmable counters
are not
fast
enough;
or,
the
counters
that are
fast
enough
lack
the
programming
capability.
One
way
of
getting
around
this
dilemma
is
to
combine
the
talents
4 Df
a
high
speed counter
with those
of
a
programmable
count-
er.
Figure
1
shows
such
a
combination, with
a
UHF
prescaler
and
a
programmable
counter
(the
"units"
decade) cooperat-
ing
in
a
pulse
swallowing*
scheme
to
simulate
a
program-
mable
UHF
decade.
in
a
pulse
swallowing
counter.
The
built-in
flexibility of
th^Se
circuits
is
at
the
expense
of
speed,
due
to
the
auxiliary
gatin
g,
the
full
synchronism,
and
the
time
required
to
do
the
hous^.
keeping.
Figure
3
illustrates a
conventional
divider
using the
fully
pro-
grammable
circuits.
The
TC
output
of
the
first
decade
is
des-
ignated
f
2
and
gates the
f-|
pulses
into
the
second
stageThe
TC
of
the
second
stage
is
the
final
output
f
3
and
also
the
PE
signal
for
both
stages.
Following
a Preset,
the
first
stage pro-
duces an
f
2
pulse (one
f*|
period
wide)
after
the
first
K
putsos
of
f-j
and
thereafter
produces
one
f
2
pulse
for
every
10
f
pulses.
The
second
stage,
which
could as
easily
be
two
or
more
decades, produces
an output
pulse
for
every
10
pulses
of
f
2
-
Treated as
a
system
building
block,
the
overall
divide
ratio
N
can be expressed
as
follows.
Pulse
swallowing has been
described as
a
way
of
combining
a
counter
that
is
very
fast,
but rather
dumb,
with
a
counter
that
is
very
smart,
but
rather slow,
to
make
the
rest of
the
logic
think that
there
is
a
very
fast,
very
smart counter up
front.
For
purposes
of
discussion,
a
smart counter
is
defined
as
one
that
is
fully
programmable and
directly
or
indirectly
satisfies
a
few
other
requirements.
Examples
are the
10010/
16 and
95010/16 ECL
circuits
and
the
93S10/16 TTL
ele-
ments
illustrated
in
Figure
2.
Each
circuit
has
a
Terminal
Count
(TC)
output
which
is
normally
in
the
inactive state
and
goes
to
the active
state
(LOW
for
ECL,
HIGH
for
TTL)
when
the
circuit
reaches
its
maximum
count,
and
stays active
as
long
as
the
circuit retains
the
maxirnum
count.
Each
circuit
has
an
active-LOW
Parallel
Enable
(PE)
input
and
Individual
Preset data
(Pp)
inputs
for
the
four
flip-flops.
A
LOW
signal
on
PB
inhibits
counting and
enables
synchronous
presetting.
A
Count
Enable (CE)
input
can prevent counting
but
cannot
prevent
presetting.
Thus
the
synchronous
operating
modes
of
these
circuits
are
Count
Up, Hold
and
Preset,
all
of
which
are
utilized
in
either
a
straightforward
programmable
counter
or
N =
K+10(M)
(1)
For
changing
the
overall divide
ratio,
K
can be
considered
a
fine
adjustment
and
M
a
course adjustment;
therefore,
the
change
in
N due
to
changes
in
K and
M
is
AN
=
AK+
10(AM)
(2)
The
fixed
ratio
counter
or
prescaler
is
at
the high
end
of
the
speed
scale,
but
at
the
low end
of
the
Intelligence
scale,
^/g-
ure
4
illustrates
a fixed
prescaler driving
a
programmable
counter.
The
fixed
prescaler takes
away some
of
the
flexi-
bility in
choosing the
overall
divide
ratio
N
and
in
the
fine
adjustment
of N,
as
shown
in
Equations
3
and
4.
N
=
P
•
M
AP
=
0
AN
=
P(AM)
(4)
pqeSET DATA
(NIN£S
COMPUMENT1
TENS
HUNORCOS
THOUSANDS
•Nichols.
J.
and
Shinn.
C..
"Pulse Swallowing".
EON. October
1.
1970.
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