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11
10
.
6
.
Test
3
(Relay
and
FET
test).
Setting
Edge
Testpoint
Signalname
start
stop
clock
qualifier
qualifier
ground
li
(neg)
J"
(pos)
S
(pos)
li
(neg)
(pos)
TP14
TPM
TP15
D1903
pin
7
D1903
pin
2
TP1
|P17l
[PIZJ
ALE
AZC/P]
AZ
Logic
0
NOTE:
The
testrom
placed
in
D
1909
socket
(Both
ROMs
removed)
2.
Short
circuit
TP10 and TP
11
3.
Reading
display:
L3
4.
Reference
logic
0
=
000
logic
1
=
593
A
09
QIS
DATA
oil
CLOCK
015
010
01
DLEN4
014
013
Q2
08
03
012
VEE
07
06
05
04
LOEX
VCC
DUP
VEE
rP2ll
*0000
D1908
SAA1060
LOGIC
0
=
0000
LOGIC
1
=593A
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