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interrupt conditions:
There
are
two modes
of
trigger
level
interrupt:
—
The
normal
trigger-mode,
where
the
signal
is
triggered
on
successive positive crossings
(or
successive negative
crossings)
of the
trigger
level.
—
The
special trigger
mode,
using
the data hold
input,
where
the
signal
is
triggered
on
successive positive
and
negative
(or
negative
and
positive) crossings
of the
trigger
level.
Considering
first,
the
normal
trigger
mode;
i.e.
with
the data hold switch
open.
As
explained, the condition for interrupt
is
a logic
'0'
on
the
INT
pin;
i.e. all
the three inputs of
NAND-gate
D1918
at logic
1
simultaneously.
Path
1
takes the
comparator output
waveform
to the
NAND-gate
input 2 of
D191
1
via a
two-input
exclusive-
OR
gate.
A
logic
'1
'
is
passed
only
when
a
'1
'
input appears
on
either
one
or
the other of the
inputs.
Two
small
RC
delays are applied to the inputs so that the inputs
arrive at slightly
different
times
after
the
start
of
the
comparator output waveform.
This
means
that for
a
short period,
i.e.
the difference
in
the delay
times,
one
of the
inputs,
the
one
with
the shorter delay
is
at logic
'1
'.
Consequently,
a logic
'1
'
appears
at
the
output
of the gate for
this
short period
until
the other input
is
at logic
'1'
;
i.e.
the condition
for
'0'
output.
At
the
end
of the
comparator
pulse,
the input
with
the shorter delay
returns to
logic
'0'
after
its
delay
time.
However,
the other input remains
at logic
'0'
for
its
delay period
and
gives
a
corresponding
logic
'1'
pulse to
the gate
output
as
shown.
Path 2
inverts
the
comparator output
waveform and
applies
it
via
a
NAND-gate
to input
8
of
D1918
in
its
original
form.
Path
3
applies
the
comparator output
via
the clock input of the
flip-flop
to the output,
which
is
applied to the
third
input 2 of the
NAND-gate.
Ail
three inputs of
NAND-gate D1918
are
at logic
'1'
during the
positive-going crossings
of the
trigger-level.
As
path 2
changes
polarity
at
the
end
of the
positive-going
comparator
pulse,
no
intermediate interrupt
pulse
occurs
in
the
normal
trigger
mode.
Considering the
special trigger
mode
the
circuit
functions
are identical,
except
that the data hold
input
puts
a
logic
'0'
on
to the input of the
NAND-gate
in
path
2.
This
means
that the output,
and consequently
input
8
of
NAND-gate
D1918,
are
permanently
at logic
'1'.
The
intermediate
pulse
from
the exclusive-OR gate
now
forces
the
output
of
NAND-gate D1918
to
logic
'0'
for
its
duration.
The outcome
is
that
the
/xP
counter
is
stopped
at
the negative
crossing
of the
trigger
level in
the
special trigger
mode. The
foregoing explanation has
assumed
that
positive trigger
has
been
selected.
When
negative
trigger
is
selected,
the
start
point
is
a
negative-crossing
of the
trigger
level
and
the stop
point,
a
positive
crossing
of the
trigger
level.
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