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Motorola Semiconductor MC68HC11F1 Technical Manual

8-bit microcontroller
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MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
Technical Summary
8-Bit Microcontroller

1 Introduction

The MC68HC11F1 is a high-performance member of the M68HC11 family of microcontroller units
(MCUs). High-speed expanded systems required the development of this chip with its extra input/output
(I/O) ports, an increase in static RAM (one Kbyte), internal chip-select functions, and a non-multiplexed
bus which reduces the need for external interface logic. The timer, serial I/O, and analog-to-digital (A/
D) converter enable functions similar to those found in the MC68HC11E9.
The MC68HC11FC0 is a low cost, high-speed derivative of the MC68HC11F1. It does not have
EEPROM or an analog-to-digital converter. The MC68HC11FC0 can operate at bus speeds as high as
six MHz.
This document provides a brief overview of the structure, features, control registers, packaging infor-
mation and availability of the MC68HC11F1 and MC68HC11FC0. For detailed information on
M68HC11 subsystems, programming and the instruction set, refer to the M68HC11 Reference Manual
(M68HC11RM/AD).

1.1 Features

• MC68HC11 CPU
• 512 Bytes of On-Chip Electrically Erasable Programmable ROM (EEPROM) with Block Protect
(MC68HC11F1 only)
• 1024 Bytes of On-Chip RAM (All Saved During Standby)
• Enhanced 16-Bit Timer System
— 3 Input Capture (IC) Functions
— 4 Output Compare (OC) Functions
— 4th IC or 5th OC (Software Selectable)
• On-Board Chip-Selects with Clock Stretching
• Real-Time Interrupt Circuit
• 8-Bit Pulse Accumulator
• Synchronous Serial Peripheral Interface (SPI)
• Asynchronous Nonreturn to Zero (NRZ) Serial Communication Interface (SCI)
• Power saving STOP and WAIT Modes
• Eight-Channel 8-Bit A/D Converter (MC68HC11F1 only)
• Computer Operating Properly (COP) Watchdog System and Clock Monitor
• Bus Speeds of up to 6 MHz for the MC68HC11FC0 and up to 5 MHz for the MC68HC11F1
• 68-Pin PLCC (MC68HC11F1 only), 64-Pin QFP (MC68HC11FC0 only), and 80-pin TQFP pack-
age options
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© MOTOROLA INC., 1997
Order this document
by MC68HC11FTS/D
MC68HC11F1
MC68HC11FC0

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Summary of Contents for Motorola Semiconductor MC68HC11F1

  • Page 1: Introduction

    • Bus Speeds of up to 6 MHz for the MC68HC11FC0 and up to 5 MHz for the MC68HC11F1 • 68-Pin PLCC (MC68HC11F1 only), 64-Pin QFP (MC68HC11FC0 only), and 80-pin TQFP pack- age options This document contains information on a new product. Specifications and information herein are subject to change without notice. © MOTOROLA INC., 1997...

  • Page 2: Ordering Information

    68-Pin Plastic Leaded Chip –40 ° to +85 ° C Carrier (PLCC) 3 MHz MC68L11F1CFN3 0 ° to +70 ° C 3 MHz MC68L11F1PU3 80-Pin Thin Quad Flat Pack –40 ° to +85 ° C (TQFP) 3 MHz MC68L11F1CPU3 MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 3 Table 4 MC68HC11FC0 Extended Voltage (3.0 to 5.5 V) Device Ordering Information Package Temperature Frequency MC Order Number 3 MHz MC68L11FC0FU3 64-Pin Quad Flat Pack (QFP) 4 MHz MC68L11FC0FU4 –0 ° to +70 ° C 3 MHz MC68L11FC0PU3 80-Pin Thin Quad Flat Pack (TQFP) 4 MHz MC68L11FC0PU4 MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...

  • Page 4: Table Of Contents

    Analog-to-Digital Converter 11.1 Input Pins ..........................54 11.2 Conversion Sequence .......................54 11.3 A/D Registers ..........................55 Main Timer 12.1 Timer Operation ........................57 12.2 Timer Registers .........................59 Pulse Accumulator 13.1 Pulse Accumulator Block Diagram ....................64 13.2 Pulse Accumulator Registers ....................64 MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 5 TI4O5 ....Timer Input Capture 4/Output Compare 5 ....$101E, $101F ....60 TIC1–TIC3... Timer Input Capture ............$1010–$1015 ....60 TMSK1 ....Timer Interrupt Mask 1 ..........$1022 ......61 TMSK2 ....Timer Interrupt Mask 2 ..........$1024 ....62 TOC1–TOC4 ..Timer Output Compare ..........$1016–$101D ....60 MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...

  • Page 6: Block Diagrams

    SYSTEM OC4/OC1 IC4/OC5/OC1 PERIODIC INTERRUPT 512 BYTES EEPROM CSPROG CSGEN CSIO1 CSIO2 1024 BYTES STATIC RAM CHIP SELECTS CORE ADDRESS BUS DATA BUS MISO MOSI PORT C PORT B PORT F DDRC Figure 1 MC68HC11F1 Block Diagram MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 7 CSGEN OC2/OC1 CSIO1 TIMER OC3/OC1 CSIO2 SYSTEM OC4/OC1 IC4/OC5/OC1 CHIP PERIODIC INTERRUPT SELECTS WAIT 1024 BYTES STATIC RAM MISO MOSI CORE ADDRESS BUS DATA BUS PORT C PORT B PORT F DDRC Figure 2 MC68HC11FC0 Block Diagram MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...

  • Page 8: Pin Assignments And Signal Descriptions

    PE4/AN4 PC2/DATA2 PE0/AN0 PC3/DATA3 PF0/ADDR0 PC4/DATA4 PF1/ADDR1 PC5/DATA5 PF2/ADDR2 PC6/DATA6 PF3/ADDR3 PC7/DATA7 PF4/ADDR4 RESET PF5/ADDR5 MC68HC11F1 XIRQ PF6/ADDR6 PF7/ADDR7 PG7/CSPROG PB0/ADDR8 PG6/CSGEN PB1/ADDR9 PG5/CSIO1 PB2/ADDR10 PG4/CSIO2 PB3/ADDR11 PB4/ADDR12 PB5/ADDR13 PB6/ADDR14 Figure 3 MC68HC11F1 68-Pin PLCC Pin Assignments MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 9 PG4/CSIO2 PB3/ADDR11 PG5/CSIO1 PB2/ADDR10 PG6/CSGEN PB1/ADDR9 PG7/CSPROG PB0/ADDR8 PF7/ADDR7 XIRQ MC68HC11F1 PF6/ADDR6 RESET PF5/ADDR5 PC7/DATA7 PF4/ADDR4 PC6/DATA6 PF3/ADDR3 PC5/DATA5 PF2/ADDR2 PC4/DATA4 PF1/ADDR1 PC3/DATA3 PF0/ADDR0 PC2/DATA2 PE0/AN0 PC1/DATA1 PE4/AN4 Figure 4 Pin Assignments for the MC68HC11F1 80-Pin QFP MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...

  • Page 10: Mc68Hc11Fc0 Pin Assignments

    2.2 MC68HC11FC0 Pin Assignments PB6/ADDR14 PB5/ADDR13 PG4/CSIO2 PB4/ADDR12 PB3/ADDR11 PG5/CSIO1 PB2/ADDR10 PG6/CSGEN PB1/ADDR9 PG7/CSPROG PB0/ADDR8 XIRQ PF7/ADDR7 MC68HC11FC0 PF6/ADDR6 RESET PC7/DATA7 PF5/ADDR5 PF4/ADDR4 PC6/DATA6 PF3/ADDR3 PC5/DATA5 PC4/DATA4 PF2/ADDR2 PF1/ADDR1 PC3/DATA3 PF0/ADDR0 PC2/DATA2 PC1/DATA1 Figure 5 MC68HC11FC0 64-Pin QFP Pin Assignments MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 11 PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PG4/CSIO0 PB3/ADDR11 PG5/CSIO1 PB2/ADDR10 PG6/CSGEN PB1/ADDR9 PG7/CSPROG PB0/ADDR8 XIRQ PF7/ADDR7 MC68HC11FC0 PF6/ADDR6 RESET PF5/ADDR5 PC7/DATA7 PF4/ADDR4 PC6/DATA6 PF3/ADDR3 PC5/DATA5 PF2/ADDR2 PC4/DATA4 PF1/ADDR1 PC3/DATA3 PF0/ADDR0 PC2/DATA2 PC1/DATA1 Figure 6 MC68HC11FC0 80-Pin TQFP Pin Assignments MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...

  • Page 12: Pin Descriptions

    These pins provide the reference voltage for the analog-to-digital converter. Use bypass capacitors to minimize noise on these signals. Any noise on V and V will directly affect A/D accuracy. These pins are not present on the MC68HC11FC0. MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 13 PF[7:0]. In expanded mode, port F pins act as the low-order address outputs ADDR[7:0]. Port G Pins Port G is an 8-bit general-purpose I/O port. When enabled, four chip select signals are alternate functions of PG[7:4]. NOTE PG[1:0] are not available on the 64-pin MC68HC11FC0. MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...

  • Page 14: Control Registers

    Bit 8 TOC4 (High) $101D Bit 7 Bit 0 TOC4 (Low) $101E Bit 15 Bit 8 TI4/O5 (High) $101F Bit 7 Bit 0 TI4/O5 (Low) $1020 TCTL1 $1021 EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A TCTL2 MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 15 $105C I01SA I01SB I02SA I02SB GSTHA GSTGB PSTHA PSTHB CSSTRH $105D I01EN I01PL I02EN I02PL GCSPR PCSEN PSIZA PSIZB CSCTL $105E GA15 GA14 GA13 GA12 GA11 GA10 CSGADR $105F I01AV I02AV GNPOL GAVLD GSIZA GSIZB GSIZC CSGSIZ MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...

  • Page 16: Mc68Hc11Fc0 Control Registers

    EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A TCTL2 $1022 OC1I OC2I OC3I OC4I I4/O5I IC1I IC2I IC3I TMSK1 $1023 OC1F OC2F OC3F OC4F I4/O5F IC1F IC2F IC3F TFLG1 $1024 RTII PAOVI PAII TMSK2 $1025 RTIF PAOVF PAIF TFLG2 MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 17 $105C I01SA I01SB I02SA I02SB GSTHA GSTGB PSTHA PSTHB CSSTRH $105D I01EN I01PL I02EN I02PL GCSPR PCSEN PSIZA PSIZB CSCTL $105E GA15 GA14 GA13 GA12 GA11 GA10 CSGADR $105F I01AV I02AV GNPOL GAVLD GSIZA GSIZB GSIZC CSGSIZ MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...

  • Page 18: Operating Modes And System Initialization

    ROM. In this mode, the user can download a program into on-chip RAM through the serial communica- tion interface (SCI). Special test mode, a variation of expanded mode, is primarily used during Motorola’s internal production testing, but can support emulation and debugging during program development.

  • Page 19: Memory Maps

    4. In special test mode the address locations $zD00—$zDFF are not externally addressable. “z” represents the val- ue of bits EE[3:0] in the CONFIG register. 5. EEPROM can be remapped to any 4-Kbyte boundary ($z000). “z” represents the value contained in EE[3:0] in the CONFIG register. Figure 7 MC68HC11F1 Memory Map MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...

  • Page 20: System Initialization Registers

    INIT register. Figure 8 MC68HC11FC0 Memory Map 4.3 System Initialization Registers HPRIO — Highest Priority Interrupt and Miscellaneous $x03C Bit 7 Bit 0 RBOOT SMOD PSEL3 PSEL2 PSEL1 PSEL0 RESET: Single-Chip Expanded Bootstrap Special Test MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 21 REG[1:0] — Register Block Map Position These bits determine the location of the register block, as shown in Table 9. Table 9 Register Block Location REG[1:0] Register Block Address $0000 – $005F $1000 – $105F $2000 – $205F $3000 – $305F MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...
  • Page 22 $F000-$F05F OPT2 — System Configuration Option Register 2 $x038 Bit 7 Bit 0 GWOM CWOM CLK4X LIRDV — SPRBYP — — RESET GWOM — Port G Wired-OR Mode Option Refer to 7.8 Parallel I/O Registers, page 36. MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 23 STOP instruction and rewritten to one after recovery from STOP. FCME should be kept cleared if the user intends to use the STOP instruction. CR[1:0] — COP Timer Rate Select Refer to 5.2 Reset and Interrupt Registers, page 27. MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...
  • Page 24 1 = Generate an immediate COP failure reset. Note that the NOCOP bit in the CONFIG register must be cleared (COP enabled) in order to force the reset. Bit 0 — Not implemented. Reads always return zero and writes have no effect. MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...

  • Page 25: Resets And Interrupts

    SCI data register. It is precisely these two steps that are required to clear the RDRF flag, so no further instructions are necessary. 5.1 Interrupt Sources The following table summarizes the interrupt sources, vector addresses, masks, and flag bits. MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...

  • Page 26: Reset And Interrupt Registers

    *Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes. Bits [7:6], [4:2] Refer to 4.3 System Initialization Registers, page 23, and 11.3 A/D Registers, page 56. IRQE — IRQ Select Edge Sensitive Only 0 = Low level recognition 1 = Falling edge recognition MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 27 Pulse Accumulator Input Edge 0011 SPI Serial Transfer Complete 0100 SCI Serial System 0101 Reserved (Default to IRQ) 0110 IRQ (External Pin) 0111 Real-Time Interrupt 1000 Timer Input Capture 1 1001 Timer Input Capture 2 1010 Timer Input Capture 3 MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...
  • Page 28 Bit 0 NOCOP EEON RESET Bits 7:3, 1:0 — See 6.2 EEPROM Registers, page 30. NOCOP — COP System Disable 0 = COP enabled (forces reset on time-out) 1 = COP disabled (does not force reset on time-out) MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...

  • Page 29: Electrically Erasable Programmable Rom

    Block protect register bits can be written to zero (protection disabled) only once within 64 cycles of a reset in normal modes, or at any time in special modes. Block protect register bits can be written to one (protection enabled) at any time. MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...
  • Page 30 Bit 3 — Not implemented. Reads always return one and writes have no effect. NOCOP — COP System Disable 0 = COP enabled (forces reset on time-out) 1 = COP disabled (does not force reset on time-out) MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...

  • Page 31: Eeprom Programming And Erasure

    The following example shows how to bulk erase the 512-byte EEPROM. The CONFIG register is not affected in this example. Note that when the CONFIG register is bulk erased, CONFIG and the 512-byte array are all erased. BULKE LDAB #$06 ERASE=1, EELAT=1, EEPGM=0 STAB $103B Set EELAT bit MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...

  • Page 32: Config Register Programming

    The new value will not take effect until after the next reset se- quence. 1. Erase the CONFIG register. 2. Program the new value to the CONFIG address. 3. Initiate reset. MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...

  • Page 33: Parallel Input/Output

    64-pin MC68HC11FC0. 7.6 Port F Port F is an eight-bit output-only port. In single-chip mode, port F pins are general-purpose output pins PF[7:0]. In expanded mode, port F pins act as low-order address outputs ADDR[7:0]. MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...

  • Page 34: Port G

    PORTG — Port G Data Register $x002 Bit 7 Bit 0 PG1* PG0* RESET: Alternate CSPROG CSGEN CSIO1 CSIO2 Function: *These bits are not present on the 64-pin QFP version of the MC68HC11FC0. I = Indeterminate value MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 35 The R/W signal is used to control the direction of data transfers. DDRC — Port C Data Direction Register $x007 Bit 7 Bit 0 DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 RESET: For DDRx bits, 0 = input and 1 = output. MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...
  • Page 36 SPRBYP — — RESET GWOM — Port G Wired-OR Mode Option This bit affects all port G pins together. 0 = Port G outputs are normal CMOS outputs 1 = Port G outputs act as open-drain outputs MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 37 LIRDV — Load Instruction Register Driven Refer to 4.3 System Initialization Registers, page 23 Bits 3, 1, 0 — Not implemented. Reads always return zero and writes have no effect. SPRBYP — Refer to 10.2 SPI Registers, page 52. MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...

  • Page 38: Chip-Selects

    IO2SA, IO2SB — I/O Chip-Select 2 Clock Stretch GSTHA, GSTHB — General-Purpose Chip-Select Clock Stretch PSTHA, PSSTHB — Program Chip-Select Clock Stretch Each pair of bits selects the number of clock cycles of stretch for the corresponding chip select. MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 39 On-Chip RAM Bootloader ROM Bootloader ROM On-Chip EEPROM On-Chip EEPROM I/O Chip Selects I/O Chip Selects Program Chip Select General-Purpose Chip Select General-Purpose Chip Select Program Chip Select NOTES: 1. EEPROM is present on the MC68HC11F1 only. MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...
  • Page 40 0 = CSIO1 is valid during E-clock valid time (E-clock high) 1 = CSIO1 is valid during address valid time IO2AV — I/O Chip-Select 2 Address Valid 0 = CSIO2 is valid during E-clock valid time (E-clock high) 1 = CSIO2 is valid during address valid time MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 41 GSIZ[A:C] — Block Size for CSGEN Refer to Table 20 for bit values. Table 20 General-Purpose Chip Select Size Control GSIZ[A:C] Address Size 64 Kbytes 32 Kbytes 16 Kbytes 8 Kbytes 4 Kbytes 2 Kbytes 1 Kbyte 0 Kbytes (disabled) MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...

  • Page 42: Serial Communications Interface (Sci)

    AND CONTROL FORCE PIN DIRECTION (OUT) TRANSMITTER CONTROL LOGIC SCSR1 SCI STATUS 1 SCCR1 SCI CONTROL 1 TDRE TCIE SCCR2 SCI CONTROL 2 SCI Rx SCI INTERRUPT INTERNAL QUESTS REQUEST DATA BUS Figure 9 SCI Transmitter Block Diagram MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 43 WAKEUP LOGIC SCCR1 SCI CONTROL 1 SCSR1 SCI STATUS 1 SCDR Rx BUFFER (READ ONLY) RDRF IDLE ILIE SCCR2 SCI CONTROL 2 SCI Tx SCI INTERRUPT INTERNAL REQUESTS REQUEST DATA BUS Figure 10 SCI Receiver Block Diagram MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...

  • Page 44: Sci Registers

    16X receiver baud rate clock. The SCR[2:0] bits are not affected by reset and can be changed at any time. They should not be changed, however, when an SCI transfer is in progress. MOTOROLA MC68HC11F1/FC0...
  • Page 45 ÷ 2 0:1:0 ÷ 2 0:1:1 ÷ 2 1:0:0 ÷ 2 1:0:1 ÷ 2 1:1:0 ÷ 2 1:1:1 SCI Receive Baud Rate (16x) ÷ 16 SCI Transmit Baud Rate (1x) Figure 11 SCI Baud Rate Generator Block Diagram MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...
  • Page 46 When TE goes from zero to one, one unit of idle character time (logic one) is queued as a preamble. 0 = Transmitter disabled 1 = Transmitter enabled RE — Receiver Enable 0 = Receiver disabled 1 = Receiver enabled MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 47 FE is set when a zero is detected where a stop bit was expected. Clear the FE flag by reading SCSR with FE set and then reading SCDR. 0 = Stop bit detected 1 = Zero detected MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...
  • Page 48 Bit 0 Bit 7 Bit 0 RESET: I = Indeterminate value Reading SCDR retrieves the last byte received in the receive data buffer. Writing to SCDR loads the transmit data buffer with the next byte to be transmitted. MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...

  • Page 49: Serial Peripheral Interface

    DWOM SPIE SPI INTERRUPT MSTR CONTROL REQUEST CPHA MSTR CPOL SPR1 SPR0 SPR0 ÷2 SPR1 ÷4 INTERNAL MCU CLOCK ÷16 ÷32 CLOCK LOGIC MOSI SPRBYP MISO 8-BIT SHIFT REGISTER READ DATA BUFFER Figure 12 SPI Block Diagram MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...

  • Page 50: Spi Registers

    SCK CYCLE # (FOR REFERENCE) SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE INPUT (CPHA = 0) DATA OUT SAMPLE INPUT (CPHA = 1) DATA OUT SS (TO SLAVE) Figure 13 SPI Data Clock Timing Diagram MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 51 Bits [3:0] — Not Implemented. Reads always return zero and writes have no effect. SPDR — SPI Data Register $x02A Bit 7 Bit 0 Bit 7 Bit 0 Incoming SPI data is double buffered. Outgoing SPI data is single buffered. MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...
  • Page 52 When the SPI baud rate counter is bypassed, the SPI can transmit at a maximum master mode baud rate equal to the E-clock frequency. SPRBYP is present only on the MC68HC11FC0 and overrides the setting of SPR[1:0] in SPCR. MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...

  • Page 53: Analog-To-Digital Converter

    REGISTER AND CONTROL RESULT ANALOG INTERNAL DATA BUS ADCTL A/D CONTROL RESULT REGISTER INTERFACE ADR1 A/D RESULT 1 ADR2 A/D RESULT 2 ADR3 A/D RESULT 3 ADR4 A/D RESULT 4 EA9 A/D BLOCK Figure 14 A/D Converter Block Diagram MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...

  • Page 54: Input Pins

    12 E CYCLES CYCLES SAMPLE ANALOG INPUT SUCCESSIVE APPROXIMATION SEQUENCE CONVERT FIRST CONVERT SECOND CONVERT THIRD CONVERT FOURTH CHANNEL, UPDATE CHANNEL, UPDATE CHANNEL, UPDATE CHANNEL, UPDATE ADR1 128 — E CYCLES ADR2 ADR3 ADR4 Figure 16 A/D Conversion Sequence MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...

  • Page 55: A/D Registers

    Result in ADRx if MULT = 1 CD:CC:CB:CA 0000 ADR1 0001 ADR2 0010 ADR3 0011 ADR4 0100 ADR1 0101 ADR2 0110 ADR3 0111 ADR4 10XX Reserved ADR1–ADR4 1100 ADR1 1101 ADR2 1110 ADR3 1111 ADR4 Reserved NOTES: 1. Used for factory testing. MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...
  • Page 56 1 = A/D powered up CSEL — Clock Select 0 = A/D and EEPROM use system E-Clock 1 = A/D and EEPROM use internal RC clock Bits [5:0] — Refer to 4.3 System Initialization Registers, page 23. MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...

  • Page 57: Main Timer

    43.691 ms 174.763 ms 699.051 ms 4 MHz 8.192 ms 32.768 ms 131.072 ms 524.288 ms 5 MHz 6.554 ms 26.214 ms 104.858 ms 419.430 ms 6 MHz 5.461 ms 21.845 ms 87.381 ms 349.525 ms Any E MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...
  • Page 58 (HI) TIC3 (LO) Port A TFLG 1 TMSK 1 Control Status Interrupt (Note 1) Flags Enables IC/OC BLOCK NOTE: Registers that control port A action include DDRA, OC1M, OC1D, PACTL, TCTL1 and TCTL2. Figure 17 Main Timer MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...

  • Page 59: Timer Registers

    (MSB) first. A read of this address causes the least significant byte to be latched into a buffer for the next CPU cycle so that a double-byte read returns the full 16-bit state of the counter at the time of the MSB read cycle. MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...
  • Page 60 Each OMx–OLx bit pair determines the output action taken on the corresponding OCx pin after a suc- cessful compare, as shown in Table 29. OC5 functions only if the I4/O5 bit in the PACTL register is cleared. MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 61 If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence is requested. TFLG1 — Timer Interrupt Flag 1 $x023 Bit 7 Bit 0 OC1F OC2F OC3F OC4F I4/O5F IC1F IC2F IC3F RESET: Bits in TFLG1 are cleared by writing a one to the corresponding bit positions. MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...
  • Page 62 Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position. Bits in TFLG2 are cleared by writing a one to the corresponding bit positions. TOF — Timer Overflow Flag Set when TCNT rolls over from $FFFF to $0000. MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 63 5.461 ms 10.923 ms 21.845 ms 4 MHz 2.048 ms 4.096 ms 8.192 ms 16.384 ms 5 MHz 1.638 ms 3.277 ms 6.554 ms 13.107 ms 6 MHz 1.366 ms 2.731 ms 5.461 ms 10.923 ms Any E MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...

  • Page 64: Pulse Accumulator

    TMSK2 — Timer Interrupt Mask 2 $x024 Bit 7 Bit 0 RTII PAOVI PAII RESET: Bits [7:4] in TMSK2 correspond bit for bit with flag bits in TFLG2. Setting any of these bits enables the corresponding interrupt source. MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...
  • Page 65 PAMOD — Pulse Accumulator Mode 0 = Event counter 1 = Gated time accumulation PEDGE — Pulse Accumulator Edge Control This bit has different meanings depending on the state of the PAMOD bit, as shown in Table 33. MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...
  • Page 66 The PACNT is readable even if PAI is not active in gated time accumulation mode. The counter is not affected by reset and can be read or written at any time. Counting is synchronized to the internal PH2 clock so that incrementing and reading occur during opposite half cycles. MOTOROLA MC68HC11F1/FC0 MC68HC11FTS/D...

  • Page 67: Mc68Hc11F1/Fc0 Motorola Mc68Hc11Fts/D

    MC68HC11F1/FC0 MOTOROLA MC68HC11FTS/D...
  • Page 68 Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur.

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